Journal Publication

  1. Tsai-Ming Huang, Chun-I Lu, Ming-Chun Hong, Yu-Hsin Tseng, Kuan-Yu Liu, Wei-Ning Chang, Kun-Jen Hsueh, Meng-Chen Lu, Wei-Kai Yu, Chuang-Ju Lin, Chien-Chung Hsu, Chao-Cheng Lin, Tuo-Hung Hou, “Edge stoichiometry and percolation-governed two-dimensional scaling in amorphous IGZO transistors.” Nanoscale Horiz. 2026; DOI: 10.1039/d6nh00214e
  2. Yihan He, Ming-Chun Hong, Wanli Zheng, Ching Shih, Hsin-Han Lee, Yu-Chen Hsin, Jeng-Hua Wei, Xiao Gong, Tuo-Hung Hou & Gengchiau Liang. “Solving Boolean Satisfiability problems using a hypergraph-based probabilistic computer.” npj Unconv. Comput. 3, 39 (2026).
  3. Chen-Yi Cho, Ming-Hung Wu, Yu-De Lin, Po-Chun Yeh, Kai Ni, Wen-Yueh Jang, Tuo-Hung Hou, “Disturb-Resilient and Wake-up-Free 2T-MFMFET Array for Storage and Computing Applications.” Advanced Materials Technologies (2026): e71203. https://doi.org/10.1002/admt.71203
  4. C.-H. Liu, K. -Y. Hsiang, F. -S. Chang, M. Januar, Y.-T. Chang, C. W. Liu, T.-H. Hou, M. H. Lee, Antiferroelectric-Based Memcapacitor and Strategy for Non-Destructive Read Operation by Endurance Recovery,” in IEEE Electron Device Letters, vol. 47, no. 6, pp. 1101-1104, June 2026, doi: 10.1109/LED.2026.3684849.
  5. Wen-Jer Tsai, Chun-Chang Lu, Ting-En Hsieh, Tao-Cheng Lu, Kuang-Chao Chen, Tuo-Hung Hou, Chih-Yuan Lu, “A Page-Buffer and Fail-Bit Counter-Based In-Memory Computing Platform for 3-D NAND Flash Memory,” in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 16, no. 2, pp. 617-628, June 2026, doi: 10.1109/JETCAS.2026.3659465.
  6. Y.-L. Chou, W. -J. Tsai, T. C. Lu, K. C. Chen, T. E. Hsieh, T. H. Hou, C. Y. Lu., “A Robust Read-Based PUF Generation Method in a 3-D NAND Flash Memory,” in IEEE Transactions on Electron Devices, vol. 73, no. 3, pp. 1309-1315, March 2026.
  7. Ming‐Chun Hong, Chen‐Yu Yang, Hsin‐Han Lee, Guan‐Long Chen, Ching Shih, Yu‐Chen Hsin, Chiao‐Yun Lo, Sin‐You Huang, Cheng‐Yi Shih, Shan‐Yi Yang, I‐Jung Wang, Yao‐Jen Chang, Shih‐Ching Chiu, Yi‐Hui Su, Chih‐Yao Wang, Kuan‐Ming Chen, Ho‐Lin Tsai, Jeng‐Hua Wei, Shyh‐Shyuan Sheu, Wei‐Chung Lo, Shih‐Chieh Chang, Tuo‐Hung Hou, “High Perpendicular Anisotropy in Mo-Inserted Mg Composite Free Layer for Nonvolatile Magnetoresistive Random Access Memory in 4K-400K Universal Temperature Applications.” Small22, no. 14 (2026): e09788.
  8. Wen-Chia Wu, Terry Y. T. Hung, Fu-Kuo Hsueh, Bo-Heng Liu, Wei-Sheng Yun, Yun-Yan Chung, Yu-Ching Wang, Ze-Rui Lin, Meng-Zhan Li, Zih-Siang Jian, Szu-Huan Hsu, Jian-Chen Tsai, Jyun-Hong Chen, Chien-Wei Chen, Yiming Li, Wen-Hao Chang, Wei-Yen Woon, Chi-Chung Kei, Tuo-Hung Hou, Chao-Ching Cheng, Iuliana P. Radu,* and Chao-Hsin Chien*,” Bismuth Confinement: A Strategy for Low Resistance and Good Thermal Endurance of Integrated Contacts to MoS2, ” ACS Nano 2026, 20, 12, 9817–9827.
  9. C.-Y. Yang, M. -C. Hong, Y. -H. Lin, C. Shih, H. -H. Lee, G. -L. Chen, Y. -C. Hsin, C. -Y. Lo, S. -Y. Huang, T. -S. Huang, C. -Y. Shih, S. -Y. Yang, I. -J. Wang, Y. -J. Chang, S. -C. Chiu, Y. -H. Su, C. -Y. Wang, K. -M. Chen, H. -L. Tsai, J. -H. Wei, S. -S. Sheu, W. -C. Lo, S. -C. Chang, T. -H. Hou, “From MRAM to SP-MTJ: Ultrathin Mo-Engineered Superparamagnetic Tunnel Junction P-Bit for Solving Combinatorial Optimization Problems,” in IEEE Journal of the Electron Devices Society, doi: 10.1109/JEDS.2026.3670175.

Conference

  1. (頂尖會議) Hong-De Lin, Yuan-Chun Su, Tzu-Chuan Su, Elia Ambrosi, Cheng-Hsien Wu, Cheng-Chen Kuo, Chih-Yu Chang, Hung-Li Chiang, Ting-Hua Wei, Yu-Wei Hsu, Ching-Shuan Huang, Sin-Yue Lee, Wei-Ning Chang, Jui-Han Fu, Vincent Tung, Jack Y-C Sun, Chenming Hu, Chih-I Wu, Chao-Cheng Lin, Tuo-Hung Hou, Xinyu Bao, Tsung-En Lee, “First Demonstration of Heterogeneous n-IGZO/p-WSe2 Integration as a Power-Performance Area Booster for BEOL Complementary Gain-Cell Memory,” 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2026, pp. 1-3, doi: 10.1109/VLSITechnologyandCir65830.2026.11577393.
  2. (頂尖會議) E. AmbrosiS. Ricci, C. C. Kuo, M. Y. Song, C. H. Wu, C. H. Lin, W. H. Lu, C. Y. Hu C. X. He, ,X. H. Huang, S. Vaziri, C. F. Hsu, H. Y. Lee, Y. J. Chen, C. C. Lin, C. Y. Lo, H. H. Lee, G. L. Chen, Y. C. Hsin, W. Y. Woon, J. H. Wei, K. S. Li, T. H. Hou, K. L. Lin, C. N. Liu, X. Y. Bao, “Scalable and Stackable 2S1M SOT-MRAM Memory Cell Enabled by Two-Terminal Write and Read SNGCT Chalcogenide Selectors,” 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2026, pp. 1-3, doi: 10.1109/VLSITechnologyandCir65830.2026.11577463.
  3. (頂尖會議) C-Y. Cho, Y. -L. Shih, M. -Y. Lao, Y. -A. Chen, Y. -D. Lin, P. -C. Yeh, S. -S. Sheu, T. -H. Hou, “Origin and Modeling of the Access-Rate-Dependent Degradation and Dual-Interface Optimization in Ultra-Thin Nanolaminate HZO,” 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2026, pp. 1-3, doi: 10.1109/VLSITechnologyandCir65830.2026.11577521.
  4. M.-C. Hong, H. -H. Lee, G. -L. Chen, S. -Y. Huang, C. -Y. Lo, Y. -H. Su, H. -L. Tsai, S. -C. Chiu, C. -Y. Shih, Y. -J. Chang, C. -Y. Wang, S. -Y. Yang, Y. -C. Hsin, J. -H. Wei, S. -S. Sheu, W. -C. Lo, S. -C. Chang, T. -H. Hou, “High-RA STT-MRAM for In-Memory Computing: From Device Engineering to Prototype-IMC Validation,” 2026 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), HsinChu, Taiwan, 2026, pp. 1-2, doi: 10.1109/VLSITSA69131.2026.11527860.

US Patent

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