K.-W. Chen, S.-J. Chang, E. Y.-T. Tang, C.-P. Lin, T.-H. Hou, C.-H. Chen, and Y.-C. Tseng, “Pulse-mediated electronic tuning of the MoS2–perovskite ferroelectric field effect transistors,” ACS Appl. Electron. Mater., vol. 2, no. 12, pp. 3843-3852, Dec. 2020. [LINK]
C.-C. Chang, H.-H. Huang, B. Hudec, M.-H. Wu, C.-C. Chang, P.-T. Liu, and T.-H. Hou, ‘Strong read and write interference induced by breakdown failure in crossbar arrays,’ IEEE Trans. Elec. Dev., vol. 67, no. 12, pp. 5497−5504, Dec. 2020. [LINK]
Y.-D. Lin, P.-C. Yeh, P.-J. Tzeng, T.-H. Hou, C.-I Wu, Y.-C. King, and C.-J. Lin, ‘Promising engineering approaches for improving the reliability of HfZrOx 2D and 3D-ferrolectric random access memory,’ IEEE Trans. Elec. Dev., vol. 67, no. 12, pp. 5479−5483, Dec. 2020. [LINK]
K.-Y. Hsiang, C.-Y. Liao, K.-T. Chen, Y.-Y. Lin, C.-Y. Chueh, C. Chang, Y.-J. Tseng, Y.-J. Yang, S. T. Chang, M.-H. Liao, T.-H. Hou, C.-H. Wu, C.-C. Ho, J.-P. Chiu, C.-S. Chang, and M.-H. Lee, ‘Ferroelectric HfZrO2 with electrode engineering and stimulation schemes as symmetric analog synaptic weight element for deep neural network training,’ IEEE Trans. Elec. Dev., vol. 67, no. 10, pp. 4201−4207, Oct. 2020. [LINK]
Y.-H. Lai, R.-P. Lin, and T.-H. Hou, ‘Drain-bias transient instability of amorphous indium–gallium–zinc oxide thin-film transistors,’ IEEE Trans. Elec. Dev., vol. 67, no. 10, pp. 4526−4529, Oct. 2020. [LINK]
A. Kumar, S. S. Bezugam, B. Hudec, T. H. Hou, M. Suri, “Exploiting analog OxRAM conductance modulation for contrast enhancement application,” Electronics Letters, vol. 56, no. 12, pp. 594−597, Jun. 2020. [LINK]
B. Liu, H. H. Tai, H. Liang, E.-Y. Zheng, M. Sahoo, C.-H. Hsu, T. C. Chen, C.-A. Huang, J.-C. Wang, T.-H. Hou, C.-S. Lai, ‘Dimensional anisotropic graphene with high mobility and high on-off ratio in three-terminal RRAM device,’ Materials Chemistry Frontiers, vol. 4, pp. 1756−1763, Apr. 2020. [LINK]
Y.-W. Lan, C.-J. Hong, P.-C. Chen, Y.-Y. Lin, C.-H. Yang, C.-J. Chu, M.-Y. Li, L.-J. Li, C.-J. Su, B.-W. Wu, T.-H. Hou, K.-S. Li, and Y.-L. Zhong, ‘Nonvolatile molecular memory with the multilevel states based on MoS2 nanochannel field effect transistor through tuning gate voltage to control molecular configurations,’ Nanotechnology, vol. 31, 275204, Apr. 2020. [LINK]
S. Majumdar, Y. Chen, B. Hudec, T.-H. Hou, and M. Suri, ‘Semi-empirical RC circuit model for non-filamentary bi-layer OxRAM devices,’ IEEE Trans. Elec. Dev., vol. 67, no. 3, pp. 1348-1352, Mar. 2020. [LINK]
S. K. Kingra, V. Parmar, C.-C. Chang, B. Hudec, T.-H. Hou, and M. Suri, ‘SLIM: Simultaneous logic-in-memory computing exploiting bilayer analog OxRAM devices,’ Scientific Reports, vol. 10, 2567, 2020. [LINK]
Sk Z. Rahaman, I.-Jung Wang, D.-Y. Wang, C.-F. Pai, Y.-C. Hsin, S.-Y. Yang, H.-H. Lee, Y.-J. Chang, Y.-C. Kuo, Yi-Hui Su, G.-L. Chen, F.-M. Chen, J.-H. Wei, T.-H. Hou, S.-S. Sheu, C.-I Wu, and D.-L. Deng, ‘Size-dependent switching properties of spin-orbit torque MRAM with manufacturing-friendly 8-inch wafer-level uniformity,’ IEEE J. Elec. Dev. Soc., vol. 8, pp. 163-169, Feb. 2020. [LINK]
B. Liu, M.-C. Hong, M. Sahoo, B. L. Ong, E. S. Tok, M. Di, Y.-P. Ho, H. Liang, J.-S. Bow, Z. Liu, J.-C. Wang, T.-H. Hou, and C.-S. Lai, ‘A fluorographene-based synaptic transistor,’ Adv. Mater. Tech., 1900422, 2019. [LINK]
J.-H. Huang, H.-H. Hsu, D. Wang, W.-T. Lin, C.-C. Cheng, Y.-J. Lee, and T.-H. Hou, ‘Polymorphism control of layered MoTe2 through two-dimensional solid-phase crystallization,’ Scientific Reports, vol. 9, no. 1, 8810, Jun. 2019. [LINK]
C.-P. Lin, P.-C. Chen, J.-H. Huang, C.-T. Lin, D. Wang, W.-T. Lin, C.-C. Cheng, C.-J. Su, Y.-W. Lan, and T.-H. Hou, ‘Local modulation of electrical transport in 2D layered materials induced by electron beam irradiation,’ ACS Appl. Electron. Mater., vol. 1, no. 5, pp. 684−691, May 2019. (Cover of the Issue)[LINK]
M. Lanza, H.-S. P. Wong, E. Pop, D. Ielmini, D. Strukov, B. C. Regan, L. Larcher, M. A. Villena, J. J. Yang, L. Goux, A. Belmonte, Y. Yang, F. M. Puglisi, J. Kang, B. Magyari-Köpe, E. Yalon, A. Kenyon, M. Buckwell, A. Mehonic, A. Shluger, H. Li, T.-H. Hou, B. Hudec, D. Akinwande, R. Ge, S. Ambrogio, J. B. Roldan, E. Miranda, J. Suñe, K. L. Pey, X. Wu, N. Raghavan, E. Wu, W. D. Lu, G. Navarro, W. Zhang, H. Wu, R. Li, A. Holleitner, U. Wurstbauer, M. Lemme, M. Liu, S. Long, Q. Liu, H. Lv, A. Padovani, P. Pavan, I. Valov, X. Jing, T. Han, K. Zhu, S. Chen, F. Hui, and Y. Shi ‘Recommended methods to study resistive switching devices, ‘ Adv. Electronic Mater., vol. 5, no. 1, 1800143, Jan. 2019. [LINK]
B. Liu, Z. Liu, I.-S. Chiu, M. Di, Y. Wu, J.-C. Wang, T.-H. Hou, and C.-S. Lai, ‘Programmable synaptic metaplasticity and below femtojoule spiking energy realized in graphene-based neuromorphic memristor, ‘ ACS Appl. Mater. Inter., vol. 10, no. 24, pp. 20237-20243, Jun. 2018. [LINK]
J.-C. Liu, T.-Y. Wu, and T.-H. Hou, ‘Optimizing incremental step pulse programming for RRAM through device-circuit co-design, ‘ IEEE Trans. Circuits Syst. II Exp. Briefs, vol. 65, no. 5, pp. 617-621, May 2018. [LINK]
C.-C. Chang, P.-C. Chen, T. Chou, I-T. Wang, B. Hudec, C.-C. Chang, C.-M. Tsai, T.-S. Chang, and T.-H. Hou, ‘Mitigating asymmetric nonlinear weight update effects in hardware neural network based on analog resistive synapse,’ IEEE J. Emerg. Sel. Topics Circuits Syst., vol. 8, no. 1, pp. 116-124, Mar. 2018. [LINK]
C.-H. Lu, T.-H. Hou, T.-M. Pan, ‘High-performance double-gate a-InGaZnO ISFET pH Sensor using a HfO2 gate dielectric,’ IEEE Trans. Elec. Dev., vol. 65, no. 1, pp. 237-242. Jan. 2018. [LINK]
H.-Y. Chen, S. Brivio, C.-C. Chang, J. Frascaroli, T.-H. Hou, B. Hudec, M. Liu, H. Lv, G. Molas, J. Sohn, S. Spiga, V M. Teja, E. Vianello, and H-S P. Wong, ‘Resistive random access memory (RRAM) technology: From material, device, selector, 3D integration to bottom-up fabrication,’ J. Electroceramics, vol. 9, pp. 21-38, Dec. 2017. [LINK]
P.-S. Liu, C.-T. Lin, B. Hudec, and T.-H. Hou, ‘Internal current amplification induced by dielectric hole trapping in monolayer MoS2 transistor,’ Nanotechnology, vol. 28, 475204, Oct. 2017. [LINK]
J.-C. Liu, B. Magyari-Köpe, S. Qin, X. Zheng, H.-S. P. Wong, and T.-H. Hou, ‘AC stress and electronic effects on SET switching of HfO2 RRAM,’ Appl. Phys. Lett., vol. 111, 093502, Aug. 2017. [LINK]
J.-H. Huang, K.-Y. Deng, P.-S. Liu, C.-T. Wu, C.-T. Chou, W.-H. Chang, Y.-J. Lee, and T.-H. Hou, ‘Large-area 2D layered MoTe2 by physical vapor deposition and solid-phase crystallization in a tellurium-free atmosphere,’ Adv. Mater. Interfaces, vol. 4, 1700157, Apr. 2017. [LINK]
C.-H. Lu, T.-H. Hou, and T.-M. Pan, ‘Low-voltage InGaZnO ion-sensitive thin-film transistors fabricated by low-temperature process,’ IEEE Trans. Elec. Dev., vol. 63, no. 12, pp. 5060-5063. Dec. 2016. [LINK]
M.-J. Yu, R.-P. Lin, Y.-H. Chang, and T.-H. Hou, ‘High-voltage amorphous InGaZnO TFT with Al2O3 high-k dielectric for low-temperature monolithic 3-D integration,’ IEEE Trans. Elec. Dev., vol. 63, no. 10, pp. 3944-3949. Oct. 2016. [LINK]
F.-J. Hou, P.-J. Sung, F.-K. Hsueh, C.-T. Wu, Y.-J. Lee, Y. Li, S. Samukawa, and T.-H. Hou, ‘Suspended diamond-shaped nanowire with four {111} facets for high-performance Ge gate-all-around FETs,’ IEEE Trans. Elec. Dev., vol. 63, no. 10, pp. 3837-3843. Oct. 2016. [LINK]
I-T. Wang, C.-C. Chang, L.-W. Chiu, T. Chou, and T.-H. Hou, ‘3D Ta/TaOx/TiO2/Ti synaptic array and linearity tuning of weight update for hardware neural network applications,’ Nanotechnology, vol. 27, 365204, Aug. 2016. [LINK]
J.-H. Huang, H.-H. Chen, P.-S. Liu, L.-S. Lu, C.-T. Wu, C.-T. Chou, Y.-J. Lee, L.-J. Li, W.-H. Chang, and T.-H. Hou, ‘Large-area few-layer MoS2 deposited by sputtering,’ Material Research Express, vol. 3, 065007, June 2016. [LINK]
B. Hudec, C.-W. Hsu, I-T. Wang, W.-L. Lai, C.-C. Zhang, T. Wang, K. Frohlich, C.-H. Ho, C.-H. Lin, and T.-H. Hou, ‘3D resistive RAM cell design for high-density storage class memory-a review,’ Sci China Inf Sci, vol. 59, no. 6, 061403, June 2016. [LINK]
F.-J. Hou, P.-J. Sung, F.-K. Hsueh, C.-T. Wu, Y.-J. Lee, M.-N. Chang, Y. Li, and T.-H. Hou, ’32-nm multigate Si-nTFET with microwave-annealed abrupt junction,’ IEEE Trans. Elec. Dev., vol. 63, no. 5, pp. 1808-1813, May 2016. [LINK]
B. Hudec, I-T. Wang, W.-L. Lai, C.-C. Chang, P. Jančovič, K. Frohlich, M. Mičušík, M. Omastova, and T.-H. Hou, ‘Interface engineered HfO2-based 3D vertical ReRAM,’ J. Physics D: Appl. Phys., vol. 49, 215102, Apr. 2016. [LINK]
L.-J. Chi, M.-J. Yu, Y.-H. Chang, and T.-H. Hou, ‘1-V full-swing depletion-load a-In–Ga–Zn–O inverters for back-end-of-line compatible 3D integration,’ IEEE Electron Device Letters, vol. 37, no. 4, pp. 441-444, Apr. 2016. [LINK]
I. T. Wang and T. H. Hou, “TaOx/TiO2-based synaptic devices,” Neuro-inspired Computing Using Resistive Synaptic Devices, Springer, ISBN 9783319543130.
Conference
(Invited paper)(Keynote) T.-H. Hou, ‘Novel memory and computing platform of the future,’ 第一屆台灣量子科技共識論壇, Taipei, Taiwan, Dec. 11, 2020.
M.-H. Yan, M.-H. Wu, H.-H. Huang, Y.-H. Chen, Y.-H. Chu, T.-L. Wu, P.-C. Yeh, C.-Y. Wang, Y.-D. Lin, J.-W. Su, P.-J. Tzeng, S.-S. Sheu, W.-C. Lo, C.-I Wu, and T.-H. Hou, “BEOL-compatible multiple metal-ferroelectric-metal (m-MFM) FETs designed for low voltage (2.5 V), high density, and excellent reliability,” International Electron Devices Meeting (IEDM) 2020, pp. 75-78, San Francisco, CA, USA, Dec. 12-16, 2020.
(Invited paper) T.-H. Hou, ‘NV-BNN: Energy-efficient in-memory computing enabled by binary synaptic devices,’ International Conference on Emerging Electronics (ICEE 2020), Bangalore, India, Nov. 26-28, 2020.
R.-F. Chen, C.-P. Lin, H.-H. Hsu, and T.-H. Hou, ‘Selective semiconducting/metallic phase formation of MoTe2 via thermally-induced defect generation,’ International Electron Devices and Materials Symposia (IEDMS) 2020, Taoyuan City, Taiwan, Oct. 24–25, 2020.
S.-M. Yap, C.-C. Chang, and T.-H. Hou, ‘Tunability of spiking frequency in Ag/HfOx threshold switching selector,’ International Electron Devices and Materials Symposia (IEDMS) 2020, Taoyuan City, Taiwan, Oct. 24–25, 2020.
Y.-H. Chen, H.-H. Huang, and T.-H. Hou, ‘Ferroelectric tunnel junction based on ultra-thin Hf0.5Zr0.5O2 films,’ International Electron Devices and Materials Symposia (IEDMS) 2020, Taoyuan City, Taiwan, Oct. 24–25, 2020.
F.-X. Liang, P. Sahu, M.-H. Wu, J.-H. Wei, S.-S. Sheu, and T.-H. Hou, ‘Stochastic STT-MRAM spiking neuron circuit,’ International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2020, Hsinchu, Taiwan, Aug. 10–13, 2020.
(Invited paper) Y.-Y. Chen, C.-P. Hsu, P.-S. Liu, and T.-H. Hou, ‘Two-dimensional layered materials for artificial synapse,’ International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2020, Hsinchu, Taiwan, Aug. 10–13, 2020.
C.-P. Lin, H.-H. Hsu, and T.-H. Hou, “Phase and carrier polarity control of sputtered MoTe2 by plasma-induced defect engineering,” Device Research Conference (DRC) 2020, Columbus, Ohio, USA, Jun. 21-24, 2020.
M.-H. Wu, M.-S. Huang, Z. Zhu, F.-X. Liang, M.-C. Hong, J. Deng, J.-H. Wei, S.-S. Sheu, C.-I. Wu, G. Liang, and T.-H. Hou, ‘Compact probabilistic poisson neuron based on back-hopping oscillation in STT-MRAM for all-spin deep spiking neural network,’ Symposium on VLSI Technology and Circuits (VLSI) 2020, JFS4.2, Honolulu, HI, USA, Jun. 14-19, 2020.
S. K. Kingra, V. Parmar; S. Negi, S. Khan, B. Hudec, T.-H. Hou, and M. Suri, ‘Methodology for realizing VMM with binary RRAM arrays: Experimental demonstration of binarized-ADALINE using OxRAM crossbar,’ IEEE International Symposium on Circuits and Systems (ISCAS) 2020, Seville, Spain, May 10–21, 2020.
Y. D. Lin, H. Y. Lee, Y. T. Tang, P. C. Yeh, H. Y. Yang, P. S. Yeh, C. Y. Wang, J. W. Su, S. H. Li, S. S. Sheu, T. H. Hou, W. C. Lo, M. H. Lee, M. F. Chang, Y. C. King and C. J. Lin, “3D scalable, wake-up free, and highly reliable FRAM technology with stress-engineered HfZrOx,” International Electron Devices Meeting (IEDM) 2019, pp. 346-349, San Francisco, CA, USA, Dec. 7-11, 2019.
T.-Y. Wu, H.-H. Huang, Y.-H. Chu, C.-C. Chang, M.-H. Wu, C.-H. Hsu, C.-T. Wu, M.-C. Wu, W.-W. Wu, T.-S. Chang, H.-Y. Lee, S.-S. Sheu, W.-C. Lo, and T.-H. Hou, “Sub-nA low-current HZO ferroelectric tunnel junction for high-performance and accurate deep learning acceleration,” International Electron Devices Meeting (IEDM) 2019, pp. 118-121, San Francisco, CA, USA, Dec. 7-11, 2019.
(Invited paper) T. H. Hou, ‘Energy-efficient in-memory computing enabled by binary synaptic devices,’ IEEE International workshop on future computing (IWOFC) 2019, Hangzhou, China, Dec. 14-15, 2019.
H.-H. Huang, T.-Y. Wu, Y.-H. Chu, M.-H. Wu, C.-H. Hsu, H.-Y. Lee, S.-S. Sheu, W.-C. Lo, and T.-H. Hou, “A comprehensive modeling framework for ferroelectric tunnel junctions,” International Electron Devices Meeting (IEDM) 2019, pp. 759-762, San Francisco, CA, USA, Dec. 7-11, 2019.
(Invited paper) T. H. Hou, ‘Emerging memory for data-centric computing,’ International Workshop on Dielectric Thin Films for Future Electron Devices – Science and Technology (IWDTF) 2019, Tokyo, Japan, Nov. 18-20, 2019.
T.-H. Chung, M.-H. Wu, C.-C. Lin, K.-S. Li, and T.-H. Hou, ‘Optimization of forming scheme on RRAM crossbar array for hardware neural networks,’ International Electron Devices and Materials Symposia (IEDMS) 2019, New Taipei City, Taiwan, Oct. 24–25, 2019. (Best Paper Award)
Y.-W. Kang, C.-J. Su, and T. H. Hou, ‘New contact-first two-dimensional transistor,’ International Conference on Solid State Devices and Materials (SSDM) 2019, Nagoya, Japan, Sep. 2-5, 2019.
C.-C. Chang, C.-H. Li, T.-S. Chang, and T.-H. Hou, “STT-MRAM for deep convolutional neural network acceleration,” VLSI Design/CAD 2019, Kaohsiung, Taiwan, Aug. 6-9, 2019.
M.-H. Wu, M.-C. Hong, C.-C. Chang, P. Sahu, J.-H. Wei, H.-Y. Lee, S.-S. Sheu, and T.-H. Hou, ‘Extremely compact integrate-and-fire STT-MRAM neuron: A pathway toward all-spin artificial deep neural network,’ Symposium on VLSI Technology and Circuits (VLSI) 2019, T34, Kyoto, Japan, Jun. 9-14, 2019.
C.-C. Chang, M.-H. Wu, J.-W. Lin, C.-H. Li, V. Parmar, J.-H. Wei, H.-Y. Lee, S.-S. Sheu, M. Suri, T.-S. Chang, and T.-H. Hou, “NV-BNN: An accurate deep convolutional neural network based on binary STT-MRAM for adaptive AI edge,” Design Automation Conference (DAC) 2019, Las Vegas, NV, USA, Jun. 2-6, 2019.
Y.-W. Kang, C.-J. Su, and T. H. Hou, ‘Enhanced performance of single-layer MoS2 device by contact-first technique,’ Symposium on Nano Device Technology (SNDT) 2019, Hsinchu, Taiwan, Apr. 26, 2019. (Best Student Paper Award)
C.-C. Chang, P.-C. Chen, B. Hudec, P.-T. Liu, and T.-H. Hou, “Interchangeable Hebbian and Anti-Hebbian STDP applied to supervised learning in spiking neural network,” International Electron Devices Meeting (IEDM) 2018, pp. 356-359, San Francisco, CA, USA, Dec. 1-5, 2018.
(Invited paper) B. Hudec and T.-H. Hou, ‘Fully analog ALD-grown resistive synapses: bottom-up approach for building a neuromorphic system,’ International Conference on Emerging Electronics (ICEE 2018), Bangalore, India, Dec. 16-19, 2018.
(Invited paper) B. Hudec, C.-C. Chang, and T.-H. Hou, ‘Memristive devices by ALD: design aspects for high density 3D arrays for memory and neuromorphic applications,’ International Conference on Solid-State and Integrated Circuit Technology (ICSICT) 2018, Qingdao, China, Oct. 31-Nov. 3, 2018.
(Invited paper) T. H. Hou, ‘Cross-layer design strategy for accelerating deep learning using emerging resistive memory technology,’ 9th International Workshop on Characterization and Modeling of Memory devices, Milan, Italy, Sep. 27-28, 2018.
(Invited paper) B. Hudec, C.-C. Chang, I-T. Wang, K. Fröhlich, and T.-H. Hou, ‘Three dimensional integration of ReRAMs,’ IEEE International Conference on Nanotechnology (IEEE NANO 2018), Cork, Ireland, July 23-26, 2018.
(Invited paper) T. H. Hou, ‘Challenges and opportunities for accelerating computationally intensive deep learning using emerging resistive memory technology,’ IEEE Silicon Nanoelectronics Workshop (SNW) 2018, Honolulu, HI, USA, Jun. 17-18, 2018.
(Invited paper)(Tutorial) T. H. Hou, ‘RRAM-based neuromorphic computing: Device and algorithm co-design,’ IEEE International Memory Workshop (IMW) 2018, Kyoto, Japan, May. 13-16, 2018.
J.-C. Liu, T.-Y. Wu, and T.-H. Hou, “Optimizing incremental step pulse programming for RRAM through device-circuit co-design,” IEEE International Symposium on Circuits and Systems (ISCAS) 2018, Florence, Italy, May 27–30, 2018.
(Invited paper) T. H. Hou, ‘Large-area two-dimensional layered metal chalcogenides synthesized by sputtering and solid-phase crystallization,’ IEEE International Conference on Nano/Micro Engineered and Molecular Systems (NEMS) 2018, Singapore, Apr. 22-26, 2018.
(Invited paper) T. H. Hou, ‘Hybrid-weight Net (HW-Net) for accelerating artificial intelligence using emerging RRAM,’ Symposium on Nano Device Technology (SNDT) 2018, Hsinchu, Taiwan, Apr. 25-26, 2018.
(Invited paper) T. H. Hou, ‘Synthesizing large-area two-dimensional molybdenum ditelluride by physical vapor deposition and solid-phase crystallization,’ China Semiconductor Technology International Conference (CSTIC 2018), Shanghai, China, March 11–12, 2018.
(Invited paper) C.-C. Chang, J.-C. Liu, Y.-L. Shen, T. Chou, P.-C. Chen, I-T. Wang, C.-C. Su, M.-H. Wu, B. Hudec, C.-C. Chang, C.-M. Tsai, T.-S. Chang, H.-S. Philip Wong, and T.-H. Hou, “Challenges and opportunities toward online training acceleration using RRAM-based hardware neural network,” International Electron Devices Meeting (IEDM) 2017, pp. 278-281, San Francisco, CA, USA, Dec. 2-6, 2017.
(Invited paper) C.-C. Chang, Y.-L. Shen, P.-C. Chen, C.-C. Su, T. Chou, I-T. Wang, C.-C. Chang, B. Hudec, and T.-H. Hou, ‘A cross-layer design study of hardware neural network enabled by analog RRAM-based electronic synapse,’ MRS Fall meeting 2017, Boston, MA, USA, Nov. 26 – Dec. 1, 2017.
V. M. Teja, B. Hudec, C.-C. Chang, T.-Y. Wu, Y. Chen and T.-H. Hou, ‘Engineered resistive switching in ALD-grown Ni/HfO2/TiN RRAM devices,’ IUMRS International Conference in Asia (IUMRS-ICA) 2017, Taipei, Taiwan, Nov. 5–9, 2017.
C.-C. Chang, B. Hudec, M. Teja, Y. Chen, P.-T. Liu, and T.-H. Hou, ‘Dual-mode resistance change based on electronic switching mechanism,’ IUMRS International Conference in Asia (IUMRS-ICA) 2017, Taipei, Taiwan, Nov. 5–9, 2017.
Y. Chen, B. Hudec, C.-C. Chang, and T.-H. Hou, ‘Compact circuit model of RRAM-based synapse under arbitrary stimulation for neuromorphic computing application,’ IUMRS International Conference in Asia (IUMRS-ICA) 2017, Taipei, Taiwan, Nov. 5–9, 2017.
(Invited paper) C.-C. Chang, Y.-L. Shen, P.-C. Chen, C.-C. Su, T. Chou, I-T. Wang, C.-C. Chang, B. Hudec, and T.-H. Hou, ‘Analog RRAM-based multilayer perceptron neural network,’ Symposium on Memory Devices for Abundant Data Computing, Hong Kong, September 22–24, 2017.
C.-P. Hsu, W.-C. Liao, and T.-H. Hou, ‘Ab-initio study of interface between MoTe2 metal contacts and 2H/1T’ phases,’ International Electron Devices and Materials Symposia (IEDMS) 2017, Hsinchu, Taiwan, Sep. 7–8, 2017. (Best Paper Award)
M.-H. Wu, J.-C. Liu, M. Teja, and T.-H. Hou, ‘Interleaving testing flow on ACS test using RRAM device,’ International Electron Devices and Materials Symposia (IEDMS) 2017, Hsinchu, Taiwan, Sep. 7–8, 2017.
H.-H. Huang, T.-P. Lin, and T.-H. Hou, ‘Filamentary RRAM modelling based on kinetic Monte Carlo simulation,’ International Electron Devices and Materials Symposia (IEDMS) 2017, Hsinchu, Taiwan, Sep. 7–8, 2017.
P.-C. Chen, C.-C. Chang, and T.-H. Hou, ‘Non-ideal effects of RRAM-based neuromorphic computing system,’ International Electron Devices and Materials Symposia (IEDMS) 2017, Hsinchu, Taiwan, Sep. 7–8, 2017.
V. M. Teja, B. Hudec, C.-C. Chang, Y. Chen, and T.-H. Hou, ‘Engineering of ALD-grown CMOS compatible ReRAM,’ International Electron Devices and Materials Symposia (IEDMS) 2017, Hsinchu, Taiwan, Sep. 7–8, 2017.
(Invited paper) C.-C. Chang, Y.-L. Shen, P.-C. Chen, C.-C. Su, T. Chou, I-T. Wang, C.-C. Chang, B. Hudec, and T.-H. Hou, ‘Development of hardware neural networks based on RRAM technology,’ IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA 2017), Hsinchu, Taiwan, August 16–18, 2017.
B. Hudec, C.-C. Chang, I-T. Wang, C. Ying, V. M. Teja, and T.-H. Hou, “Fully analog ALD-grown memristor utilizing charge-trapping resistive switching,” China RRAM International Workshop, Soochow, China, Jun. 12-13, 2017.
C.-W. Hsu, X. Zheng, Y. Wu, T. H. Hou, and H.-S. P. Wong, “Statistical study of RRAM MLC set variability induced by filament morphology,” International Reliability Physics Symposium (IRPS), 5A-3, Monterey, CA, USA, Apr. 2-6, 2017.
(Invited paper) T. H. Hou, ‘Ultrathin bilayer nonlinear RRAM based on non-filamentary switching mechanism,’ China Semiconductor Technology International Conference (CSTIC 2017), Shanghai, China, March 12–13, 2017.
Y. Chen, B. Hudec, C.-C. Chang, T.-P. Lin, T. Wang, and T.-H. Hou, “Charge trapping bilayer RRAM device utilizing atomic layer deposition, International Electron Devices and Materials Symposia (IEDMS) 2016, Taipei, Taiwan, Nov. 24–25, 2016.
W.-C. Liao, C.-T. Lin, P.-S. Liu, and T.-H. Hou, “Band gap narrowing induced by H2 plasma treatment in 2D MoS2 transistor,” International Electron Devices and Materials Symposia (IEDMS) 2016, Taipei, Taiwan, Nov. 24–25, 2016.
R.-P. Lin, M.-J. Yu, Y.-H. Chang, and T.-H. Hou, “Improvement on bias stress stability of high-voltage amorphous InGaZnO thin-film transistor,” International Electron Devices and Materials Symposia (IEDMS) 2016, Taipei, Taiwan, Nov. 24–25, 2016.
C.-C. Su, Y.-L. Shen, I-T. Wang, T. Chou, L.-W. Chiu, C.-C. Chang, and T.-H. Hou, “Hardware neural network emulator: Parallel back-propagation learning for pattern recognition,” International Electron Devices and Materials Symposia (IEDMS) 2016, Taipei, Taiwan, Nov. 24–25, 2016.
T.-H. Lee, C.-T. Lin, P.-S. Liu, and T.-H. Hou, “Effects of substrate and capping layer in MoS2 ultrathin body FET,” International Electron Devices and Materials Symposia (IEDMS) 2016, Taipei, Taiwan, Nov. 24–25, 2016.
C.-C. Chang, B. Hudec, W.-C. Chang, Y. Chen, T. Wang, P.-T. Liu, and T.-H. Hou, “Defect engineering of non-filamentary Ta/HfOx/Al:TiO2/TiN RRAM,” International Electron Devices and Materials Symposia (IEDMS) 2016, Taipei, Taiwan, Nov. 24–25, 2016.
(Invited paper) I-T. Wang, T. Chou, L.-W. Chiu, C.-C. Chang, and T.-H. Hou, ‘Development of three-dimensional synaptic device and neuromorphic computing hardware,’ International Conference on Solid-State and Integrated Circuit Technology (ICSICT) 2016, Hangzhou, China, October 25-28, 2016.
(Invited paper) T. H. Hou, ‘Device design and applications of non-filamentary ALD-based bilayer RRAM,’ 6th Stanford-imec International RRAM Workshop, Stanford, CA, USA, October 10–11, 2016.
C.-C. Wan, C.-J. Su, S.-H. Hsu, G.-L. Luo, T.-H. Hou, W.-F. Wu, and W.-K. Yeh, ‘Suspended Ge gate-all-around nanowire FETs with selective etching technique,’ International Conference on Solid State Devices and Materials (SSDM) 2016, Tsukuba, Japan, Sep. 26-29, 2016.
(Invited paper) C.-P. Lin, C.-T. Lin, P.-S. Liu, M.-J. Yu, and T.-H. Hou ‘Grain size and plasma doping effects on CVD-based 2D transition metal dichalcogenide,’ IEEE International Conference on Nanotechnology (IEEE NANO 2016), pp. 501-504, Sendai City, Miyagi, Japan, August 22-25, 2016.
C.-C. Wan, G.-L. Luo, S.-H. Hsu, G.-D. Hung, C.-L. Chu, T.-H. Hou, C.-J. Su, S.-H. Chen, W.-F. Wu, and W.-K. Yeh, ‘ Suspended Ge gate-all-around nanowire nFETs with junction isolation on bulk Si,’ IEEE Silicon Nanoelectronics Workshop (SNW) 2016, Honolulu, HI, USA, Jun. 12-13, 2016.
C.-H. Lu, M.-J. Yu, Y.-H. Chang, Y.-H. Lai, P.-S. Liu, T.-H. Hou and T.-M. Pan, ‘Sub-0.5 V low-temperature a-IGZO ion-sensitive FET,’ International Symposium on Next-Generation Electronics (ISNE) 2016, Hsinchu, Taiwan, May 4–6, 2016.
M.-J. Yu, R.-P. Lin, Y.-H. Chang, and T.-H. Hou, ‘Reliable high-voltage amorphous InGaZnO TFT for monolithic 3D integration,’ International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2016, Hsinchu, Taiwan, Apr. 25–27, 2016.
US Patent
T.-H. Hou, S.-C. Pan, and P.-S. Liu, ‘Impact ionization semiconductor device and manufacturing method thereof,’ US Patent 10,868,195, Dec 10, 2020.
T.-H. Hou, S.-C. Pan, and P.-S. Liu, ‘Impact ionization semiconductor device and manufacturing method thereof,’ US Patent 10,510,903, Dec 17, 2019.
T.-H. Hou, and J.-H. Huang, ‘Fabrication method for two-dimensional materials,’ US Patent 10,428,427, Oct 11, 2019.
T.-H. Hou, B. Hudec, and C.-C. Chang, ‘Resistive random access memory having charge trapping layer, manufacturing method thereof, and operation thereof,’ US Patent 10,236,061, March 19, 2019.
T.-H. Hou, C.-W. Hsu, C.-T. Chou, and W.-L. Lai, ‘Self-rectifying RRAM cell structure having two resistive switching layers with different bandgaps and RRAM 3D crossbar array architecture,’ US Patent 10,056,432, Aug 21, 2018.
T.-H. Hou, C.-W. Hsu, and C.-T. Chou, ‘Self-rectifying resistive random access memory cell structure,’ US Patent 9,978,941, May 22, 2018.
T.-H. Hou and I-T. Wang, ‘Resistive memory apparatus and a writing method thereof,’ US Patent 9,715,931, Jul. 25, 2017.
T.-H. Hou and S. C. Pan, ‘FET device having a vertical channel in a 2D material layer,’ US Patent 9,553,199, Jan. 24, 2017.
T.-H. Hou, C.-W. Hsu, and M.-C. Chen, ‘Resistive memory apparatus and write-in method thereof,’ US Patent 9,269,434, Feb. 23, 2016.
