Journal Publication

  1. J.-J. Huang, C.-W. Kuo, W.-C. Chang, and T.-H. Hou, “Transition of stable rectification to resistive-switching in Ti/TiO2/Pt oxide diode,” Appl. Phys. Lett., vol. 96, no. 26, 262901, Jun. 2010. [LINK]
  2. C.-C. Lu, J.-J. Huang, W.-C. Luo, T.-H. Hou, and T.-F. Lei, “Characterization of highly strained nFET device performance and channel mobility with SMT,” J. Electrochem. Soc., vol. 157, no. 7, H705-H710, May. 2010. [LINK]
  3. S.-H. Wu, C.-K. Deng, T.-H. Hou, and B.-S. Chiou, “Stability of La2O3 metal-insulator-metal capacitors under constant voltage stress,” Jpn. J. Appl. Phys., vol. 49, no. 4, 04DB16, Apr. 2010. [LINK]
  4. C.-C. Lu, J.-J. Huang, W.-C. Luo, T.-H. Hou, and T.-F. Lei, “Strained silicon technology: mobility enhancement and improved short channel effect performance by stress memorization technique on nFET devices,” J. Electrochem. Soc., vol. 157, no. 5, H497-H500, Mar. 2010. [LINK]
  5. J. Shaw, T. H. Hou, H. Raza, and E. C. Kan, “Statistical metrology of metal nanocrystal memories with 3-D finite-element analysis,” IEEE Trans. Elec. Dev., vol. 56, no. 8, p.1729, Aug. 2009. [LINK]
  6. C.-C. Lu, T.-F. Lei, T.-H. Hou, C.-H. Chien, M.-H. Liao, T.-L. Lee, S.-M. Jang, “An investigation of strain silicon technology on highly strained, highly scaled nFET devices,” Int. J. Electr. Eng., vol. 16, pp. 289-294, Aug. 2009.
  7. T. H. Hou, H. Raza, K. Afshari, D. J. Ruebusch, and E. C. Kan, 2008, Apr., “Nonvolatile memory with molecule-engineered tunneling barriers,” Appl. Phys. Lett., vol. 92, no. 15, 153109, Apr. 2008 (Top 20 most downloaded in APL, April 2008) (Also appeared in Virtual Journal of Nanoscale Science & Technology). [LINK]
  8. T. H. Hou, U. Ganguly, and E. C. Kan, 2007, Feb., “Fermi-level pinning in nanocrystal memories,” IEEE Electron Device Letters, vol. 28, no. 2, pp.103-106, Feb. 2007. [LINK]
  9. U. Ganguly, C. Lee, T. H. Hou, and E. C. Kan, 2007, Jan., “Enhanced electrostatics for low-voltage operations in nanocrystal based nanotube/nanowire memories,” IEEE Trans. Nanotech., vol. 6, no. 1, pp. 22-27, Jan. 2007. [LINK]
  10. T. H. Hou, U. Ganguly, and E. C. Kan, “Programable molecular orbital states of C60 from integrated circuits,” Appl. Phys. Lett., vol. 89, no. 25, 253113, Dec. 2006 (Also appeared in Virtual Journal of Nanoscale Science & Technology). [LINK]
  11. T. H. Hou, C. Lee, V. Narayanan, U. Ganguly, and E. C. Kan, 2006, Dec., “Design optimization of metal nanocrystal memory─Part I: nanocrystal array engineering,” IEEE Trans. Elec. Dev., vol. 53, no. 12, pp.3095-3102, Dec. 2006. [LINK]
  12. T. H. Hou, C. Lee, V. Narayanan, U. Ganguly, and E. C. Kan, 2006, Dec., “Design optimization of metal nanocrystal memory─Part II: gate stack engineering,” IEEE Trans. Elec. Dev., vol. 53, no. 12, pp. 3103-3109, Dec. 2006. [LINK]
  13. U. Ganguly, V. Narayanan, C. Lee, T. H. Hou, and E. C. Kan, 2006, Jun., “Three-dimensional analytical modeling of nanocrystal memory electrostatics,” J. Appl. Phys., vol. 99, no. 11, 114516, Jun. 2006. [LINK]

Conference

  1. C. W. Hsu, C. W. Kuo, J. J. Huang, and T. H. Hou, “Development of 1D-1R TiO2 RRAM compatable with room-temperature fabrication,” International Electron Devices and Materials Symposia (IEDMS) 2010, Nov. 18–19, 2010.
  2. K. L. Lin, J. H. Lin, J. Shieh, C. T. Chou, Y. J. Lee, Y. M. Li, and T. H. Hou, “Silicon-compatable unipolar-switching Ni/HfO2/Si RRAM,” International Electron Devices and Materials Symposia (IEDMS) 2010, Taoyuan, Taiwan, Nov. 18–19, 2010.
  3. W. C. Chang, J. J. Huang, C. W. Kuo, K. L. Lin, and T. H. Hou, ”Doping effect and thermal instability of Ti:NiO resistive switching random access memory,” International Electron Devices and Materials Symposia (IEDMS) 2010, Taoyuan, Taiwan, Nov. 18–19, 2010.
  4. C. W. Kuo, J. J. Huang, W. C. Chang, and T. H. Hou, “One-diode-one-resistor titanium-oxide RRAM fabricated at room temperature,” International Conference on Solid State Devices and Materials (SSDM) 2010, Tokyo, Japan, Sep. 22-24, 2010.
  5. S. C. Wu, T. H. Hou, S. H. Chuang, H. C. Chou, P. Y. Kuo, T. S. Chao, T. F. Lei, “High-performance polycrystalline silicon thin-film transistor with nickel-titanium oxide by sol-gel spin-coating and fluorine implantation,” International Conference on Solid State Devices and Materials (SSDM) 2010, Tokyo, Japan, Sep. 22-24, 2010.
  6. W.-C. Chang, J.-J. Huang, C.-W. Kuo, G.-L. Lin, and T.-H. Hou, “Improvement of NiO resistance random access memory by high-temperature reactive sputtering,” Symposium on Nano Device Technology (SNDT) 2010, Hsinchu, Taiwan, May 4-5, 2010.
  7. S.-H. Wu, C.-K. Deng, T.-H. Hou, and B.-S. Chiou “Stability and degradation mechanism of La2O3 metal-insulator-metal capacitors under constant voltage stress,” 217th Electrochemical Society (ECS) Meeting, Vancouver, Canada, Apr. 25-30, 2010.
  8. J.-J. Huang, G.-L. Lin, C.-W. Kuo, W.-C. Chang, and T.-H. Hou, “Room-temperature TiOx oxide diode for 1D1R resistance-switching memory,” International Semiconductor Device Research Symposium (ISDRS), College Park, MA, USA, Dec. 9-11, 2009.
  9. S.-C. Wu, C. L., C.-K. Deng, T.-S. Chao, S.-H. Chuang, T.-H. Hou, and T.-F. Lei, “Characterization of polycrystalline silicon thin-film transistors with nickel-titanium oxide films by sol-gel spin-coating method,” International Electron Devices and Materials Symposia (IEDMS) 2009, Taoyuan, Taiwan, Nov. 19–20, 2009.
  10. J. Shaw, T. H. Hou, H. Raza, and E. C. Kan, “3D finite-element analysis of metal nanocrystal memories variations,” 13th International Workshop on Computational Electronics (IWCE) 2009, pp. 141-143, Beijing, China, May 27-30, 2009.
  11. H. Raza, T. Raza, T. H. Hou, and E. C. Kan, ‘Electronic-structure modulation transistor: A new switch with few kT supply voltage,’ APS March Meeting, Pittsburgh, PA, USA, Mar. 16–20, 2009 (Also appeared in arXiv:0812.0123).
  12. J. Lee, J. J. Cha, S. C. Barron, D. A. Muller, R. B. van Dover, E. K. Amponsah, T.-H. Hou, H. Raza, and E. C. Kan, “Low-temperature planar polysilicon TFT flash memory cell with single and double metal nanocrystals and Al2O3/(Ti,Dy)xOy dielectric layers for 3D integration,” IEEE International SOI Conference 2008, pp. 39-40, New Paltz, NY, USA, Oct. 06-09, 2008.
  13. T. H. Hou, H. Raza, K. Afshari, D. J. Ruebusch, and E. C. Kan, 2008, “Heterogeneous integration of molecules in nonvolatile memory,” 66th Device Research Conference, pp. 275-276, Santa Babara, CA, USA, Jun. 23-25, 2008.
  14. J. Lee, S. C. Barron, R. B. van Dover, E. K. Amponsah, T.-H. Hou, H. Raza, and E. C. Kan, “Planar poly-silicon TFT low-voltage flash memory cell with Al2O3 tunnel dielectric and (Ti,Dy)O control dielectric for three-dimensional integration,” 66nd Device Research Conference, pp. 279-280, Santa Babara, CA, USA, Jun 23-25, 2008.
  15. J. Lee, S. C. Barron, R. B. van Dover, E. K. Amponsah, T.-H. Hou, H. Raza, and E. C. Kan, “Highly stackable nonvolatile memory with ultra thin polysilicon film and low-leakage (Ti, Dy)xOy for low processing temperature and low operating voltage,” 2008 E-MRS meeting, Strasbourg, France, May 26 – 30, 2008.
  16. (Invited paper) T. H. Hou, J. Lee, J. T. Shaw, and E. C. Kan, ”Flash memory scaling: from material selection to performance improvement,” MRS spring meeting 2008, San Francisco, CA, USA, Mar. 24 – 28, 2008.
  17. T. H. Hou, C. Lee, and E. C. Kan, 2007, “Modeling of multi-layer nanocrystal memory,” 65nd Device Research Conference, pp.221-222, Notre Dame, IN, USA, Jun. 18-20, 2007.
  18. U. Ganguly, T. H. Hou, and E. C. Kan, 2006, ”Quantum transport and trap effects in tunneling rate measurements of metal nanocrystal based carbon nanotube memory,” 2006 MRS fall meeting , Boston, MA, USA, Nov. 27 – Dec. 1, 2006.
  19. U. Ganguly, T. H. Hou, and E. C. Kan, 2006, ”Process integration of composite high-k tunneling dielectric for nanocrystal based carbon nanotube memory,” 2006 MRS fall meeting , Boston, MA, Nov. 27 – Dec. 1, 2006.
  20. T. H. Hou, C. Lee, V. Narayanan, U. Ganguly, and E. C. Kan, 2006, “3-D electrostatic modeling and impact of high-k control oxide in metal nanocrystal memory,” 64nd Device Research Conference, pp.271-272, University Park, PA, USA, Jun. 26-28, 2006.

US Patent

  1. M. F. Wang, T. H. Hou, K. L. Mai, L. G. Yao, and S. C. Chen, “High-K gate dielectric stack plasma treatment to adjust threshold voltage characteristics”, US Patent 7,303,996, Dec. 4, 2007.
  2. T. H. Hou, M. F. Wang, C. C. Chen, C. W. Yang, L. G. Yao, and S. C. Chen, “Dual-gate structure and method of fabricating integrated circuits having dual-gate structures”, US Patent 7,271,450, Sep. 18, 2007.
  3. M. F. Wang, C. L. Chen, C. W. Yang, C. C. Chen, T. H. Hou, Y. M. Lin, L. G. Yao, and S. C. Chen, “Method and structure for forming high-k gates”, US Patent 7,071,066, Jul. 4, 2006.
  4. T. H. Hou, M. F. Wang, C. C. Chen, C. W. Yang, L. G. Yao, and S. C. Chen, “Dual-gate structure and method of fabricating integrated circuits having dual-gate structures”, US Patent 7,030,024, Apr. 18, 2006
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