Y. He, M.-C. Hong, W. Zheng, C. Shih, H.-H. Lee, Y.-C. Hsin, J.-H. Wei, X. Gong, T.-H. Hou & G. Liang. “Solving Boolean Satisfiability problems using a hypergraph-based probabilistic computer.” npj Unconv. Comput.3, 39 (2026). [LINK]
C.-Y. Cho, M.-H. Wu, Y.-D. Lin, P.-C. Yeh, K. Ni, W.-Y. Jang, T.-H. Hou, “Disturb-Resilient and Wake-up-Free 2T-MFMFET Array for Storage and Computing Applications.” Advanced Materials Technologies (2026): e71203. [LINK]
C.-H. Liu, K. -Y. Hsiang, F. -S. Chang, M. Januar, Y.-T. Chang, C. W. Liu, T.-H. Hou, M. H. Lee, “Antiferroelectric-Based Memcapacitor and Strategy for Non-Destructive Read Operation by Endurance Recovery,” in IEEE Electron Device Letters, vol. 47, no. 6, pp. 1101-1104, June 2026, doi: 10.1109/LED.2026.3684849. [LINK]
W. -J. Tsai, C. -C. Lu, T. -E. Hsieh, T. -C. Lu, K. -C. Chen, T. -H. Hou, C. -Y. Lu, “A Page-Buffer and Fail-Bit Counter-Based In-Memory Computing Platform for 3-D NAND Flash Memory,” in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 16, no. 2, pp. 617-628, June 2026, doi: 10.1109/JETCAS.2026.3659465. [LINK]
Y.-L. Chou, W. -J. Tsai, T. C. Lu, K. C. Chen, T. E. Hsieh, T. H. Hou, C. Y. Lu., “A Robust Read-Based PUF Generation Method in a 3-D NAND Flash Memory,” in IEEE Transactions on Electron Devices, vol. 73, no. 3, pp. 1309-1315, March 2026. [LINK]
M.‐C. Hong, C.‐Y. Yang, H.‐H. Lee, G.‐L. Chen, C. Shih, Y.‐C. Hsin, C.‐Y. Lo, S.‐Y. Huang, C.‐Y. Shih, S.‐Y. Yang, I‐J. Wang, Y.‐J. Chang, S.‐C. Chiu, Y.‐H. Su, C.‐Y. Wang, K.‐M. Chen, H.‐L. Tsai, J.‐H. Wei, S.‐S. Sheu, W.‐C. Lo, S.‐C. Chang, T.‐H. Hou, “High Perpendicular Anisotropy in Mo-Inserted Mg Composite Free Layer for Nonvolatile Magnetoresistive Random Access Memory in 4K-400K Universal Temperature Applications.” Small22, no. 14 (2026): e09788. [LINK]
W.-C. Wu, Terry Y. T. Hung, F.-K. Hsueh, B.-H. Liu, W.-S. Yun, Y.-Y. Chung, Y.-C. Wang, Z.-R. Lin, M.-Z. Li, Z.-S. Jian, S.-H. Hsu, J.-C.n Tsai, J.-H. Chen, C.-W. Chen, Y. Li, W.-H. Chang, W.-Y. Woon, C.-C. Kei, T.-H. Hou, C.-C. Cheng, I. P. Radu,* and C.-H. Chien*, “Bismuth Confinement: A Strategy for Low Resistance and Good Thermal Endurance of Integrated Contacts to MoS2,” ACS Nano 2026, 20, 12, 9817–9827. [LINK]
C.-Y. Yang, M. -C. Hong, Y. -H. Lin, C. Shih, H. -H. Lee, G. -L. Chen, Y. -C. Hsin, C. -Y. Lo, S. -Y. Huang, T. -S. Huang, C. -Y. Shih, S. -Y. Yang, I. -J. Wang, Y. -J. Chang, S. -C. Chiu, Y. -H. Su, C. -Y. Wang, K. -M. Chen, H. -L. Tsai, J. -H. Wei, S. -S. Sheu, W. -C. Lo, S. -C. Chang, T. -H. Hou, “From MRAM to SP-MTJ: Ultrathin Mo-Engineered Superparamagnetic Tunnel Junction P-Bit for Solving Combinatorial Optimization Problems,” in IEEE Journal of the Electron Devices Society, doi: 10.1109/JEDS.2026.3670175. [LINK]
Conference
(頂尖會議) H.-D. Lin, Y.-C. Su, .-C. Su, E. Ambrosi, C.-H. Wu, C.-C. Kuo, C.-Y. Chang, H.-L. Chiang, T.-H. Wei, Y.-W. Hsu, C.-S. Huang, S.-Y. Lee, W.-N. Chang, J.-H. Fu, V. Tung, Jack Y-C Sun, C. Hu, C.-I Wu, C.-C. Lin, T.-H. Hou, X. Bao, T.-E. Lee, “First Demonstration of Heterogeneous n-IGZO/p-WSe2 Integration as a Power-Performance Area Booster for BEOL Complementary Gain-Cell Memory,” 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2026, pp. 1-3, doi: 10.1109/VLSITechnologyandCir65830.2026.11577393.
(頂尖會議) E. AmbrosiS. Ricci, C. C. Kuo, M. Y. Song, C. H. Wu, C. H. Lin, W. H. Lu, C. Y. Hu C. X. He, ,X. H. Huang, S. Vaziri, C. F. Hsu, H. Y. Lee, Y. J. Chen, C. C. Lin, C. Y. Lo, H. H. Lee, G. L. Chen, Y. C. Hsin, W. Y. Woon, J. H. Wei, K. S. Li, T. H. Hou, K. L. Lin, C. N. Liu, X. Y. Bao, “Scalable and Stackable 2S1M SOT-MRAM Memory Cell Enabled by Two-Terminal Write and Read SNGCT Chalcogenide Selectors,” 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2026, pp. 1-3, doi: 10.1109/VLSITechnologyandCir65830.2026.11577463.
(頂尖會議) C-Y. Cho, Y. -L. Shih, M. -Y. Lao, Y. -A. Chen, Y. -D. Lin, P. -C. Yeh, S. -S. Sheu, T. -H. Hou, “Origin and Modeling of the Access-Rate-Dependent Degradation and Dual-Interface Optimization in Ultra-Thin Nanolaminate HZO,” 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2026, pp. 1-3, doi: 10.1109/VLSITechnologyandCir65830.2026.11577521.
M.-C. Hong, H. -H. Lee, G. -L. Chen, S. -Y. Huang, C. -Y. Lo, Y. -H. Su, H. -L. Tsai, S. -C. Chiu, C. -Y. Shih, Y. -J. Chang, C. -Y. Wang, S. -Y. Yang, Y. -C. Hsin, J. -H. Wei, S. -S. Sheu, W. -C. Lo, S. -C. Chang, T. -H. Hou, “High-RA STT-MRAM for In-Memory Computing: From Device Engineering to Prototype-IMC Validation,” 2026 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), HsinChu, Taiwan, 2026, pp. 1-2, doi: 10.1109/VLSITSA69131.2026.11527860.