C. -Y. Cho, C. -Y. Chiu, S. De and T. -H. Hou, “Exploring BEOL-Compatible Ferroelectricity in Ultra-Thin Hafnium Zirconium Oxide: Thermal Budget, FTJ Characteristics, and Device Reliability,” in IEEE Journal of the Electron Devices Society. [LINK]
A. Shaban, S. Gothalyan, T. -H. Hou and M. Suri, “SOT-MRAM-Based Design for Energy-Efficient and Reliable Binary Neural Network Acceleration,” in IEEE Transactions on Electron Devices, vol. 71, no. 9, pp. 5367-5374, Sept. 2024. [LINK]
A. Shaban, T. -H. Hou and M. Suri, “SOT-MRAM-Based Approximate Content Addressable Memory for DNA Classification,” in IEEE Transactions on Electron Devices, vol. 71, no. 9, pp. 5732-5738, Sept. 2024. [LINK]
C. -Y. Cho, T. -Y. Chao, T. -Y. Lin, I. -T. Wang, S. De, Y. -S. Chen, Y. -C. Ong, Y. -D. Lin, P. -C. Yeh, T. -H. Hou, “Unraveling the Wake-Up Mechanism in Ultrathin Ferroelectric Hf0.5 Zr0.5O₂: Interfacial Layer Soft Breakdown and Physical Modeling,” in IEEE Transactions on Electron Devices, vol. 71, no. 5, pp. 3365-3370, May 2024. [LINK]
K.-Y. Hsiang, F.-S. Chang, Z.-F. Lou, A. Aich, A. Senapati, J.-Y. Lee, Z.-X. Li, J.-H. Chen, C.-H. Liu, C. W. Liu, S. Maikap, P. Su, T.-H. Hou, M. H. Lee , “Unleashing Endurance Limits of Emerging Memory: Multi-Level FeRAM Recovery Array Empowered by a Coordinated Inverting Amplifier Circuit,” in IEEE Transactions on Electron Devices, vol. 71, no. 4, pp. 2708-2713, April 2024. [LINK]
C.-P. Hsu, A. Useinov, W.-Y. Woon, S. Liao, T.-H. Hou, Synthesis and Phase Transition of Large-Area Layered Ferroelectric Semiconductor α-In2Se3 via 2D Solid-Phase Crystallization. Adv. Electron. Mater. 2024, 10, 2300880. [LINK]
M. Kumar, M. -H. Wu, T. -H. Hou and M. Suri, “CMOS-RRAM Based Non-Volatile Ternary Content Addressable Memory (nvTCAM),” in IEEE Transactions on Nanotechnology, vol. 23, pp. 203-207, 2024, doi: 10.1109/TNANO.2024.3360312. [LINK]
M. Chaudhary, Y.-C. Shih, S.-Y. Tang, T.-Y. Yang, T.-W. Kuo, C.-C. Chung, Y.-C. Shen, A. K. Anbalagan, C.-H. Lee, T.-H. Hou, J.-H. He, and Y.-L. Chueh, ” Phase/interfacial-engineered two-dimensional-layered WSe2 films by a plasma-assisted selenization process: Modulation of oxygen vacancies in resistive random-access memory,” ACS Appl. Mater. Inter., vol. 15, no. 28, pp. 33858-33867, Jul. 2023. [LINK]
B. Liu, Y. Zhao, Y.-F. Chang, H. H. Tai, H. Liang, T. C. Chen, S. Feng, T.-H. Hou, and C.-S. Lai, “Implementing hardware primitives based on memristive spatiotemporal variability into cryptography applications,” Chip, vol. 2, no. 1, 100040, Mar. 2023. [LINK]
K.-Y. Hsiang, J.-Y. Lee, Z.-F. Lou, F.-S. Chang, Y.-C. Chen, Z.-X. Li, M. H. Liao, C. W. Liu, T.-H. Hou, P. Su, and M. H. Lee, “Fatigue mechanism of antiferroelectric HfZrO toward endurance immunity by opposite polarity cycling recovery (OPCR) for eDRAM,” IEEE Trans. Elec. Dev., vol. 70, no. 4, pp. 2142-2146, Apr. 2023. [LINK]
B. Liu, J. Ma, H.-H. Tai, D. Verma, M. Sahoo, Y.-F. Chang, H. Liang, S. Feng, L.-J. Li, T.-H. Hou, and C.-S. Lai, “Memristive True Random Number Generator with Intrinsic Two-Dimensional Physical Unclonable Function,” ACS Appl. Electron. Mater. 2023, 5, 2, 714–720. [LINK]
M.-H. Wu, I-T. Wang, M.-C. Hong, K.-M. Chen, Y.-C. Tseng, J.-H. Wei, and T.-H. Hou, “Stochastic switching in magnetic tunnel junction neuron and bias-dependent Néel-Arrhenius model,” Phy. Rev. Appl., 18 (6), 064034, Dec. 2022. [LINK]
W.-H. Chang, C.-I. Lu, T. H. Yang, S.-T. Yang, K. B. Simbulan, C.-P. Lin, T.-H. Hou, C.-H. Chen, T.-H. Lu and Y.-W. Lan, “Defect-engineered room temperature negative differential resistance in monolayer MoS2 transistors,” Nanoscale Horizons, 2022, 7, 1533-1539. [LINK]
H.-H. Huang, Y.-H. Chu, T.-Y. Wu, M.-H. Wu, I-T. Wang, and T.-H. Hou, “Performance enhancement and transient current response of ferroelectric tunnel junction: A theoretical study,” IEEE Trans. Elec. Dev., vol. 69, no. 8, pp. 4686-4692, Aug. 2022. [LINK]
Y.-H. Chiang, C.-E. Ni, Y. Sung, T.-H. Hou, T.-S. Chang, S.-J. Jou, “Hardware-robust in-RRAM-computing for object detection,” IEEE J. Emerg. Sel. Topics Circuits Syst., vol. 12, no. 2, pp. 547-556, May 2022. [LINK]
S.-M. Yap, I.-T. Wang, M.-H. Wu, and T.-H. Hou, “Voltage-time transformation model for threshold-switching spiking neuron based on nucleation theory,” Frontiers in Neuroscience, vol. 16, 868671, 2022. [LINK]
Y.-H. Lai, I.-T. Wang, and T.-H. Hou, “Giant photoresponsivity and external quantum efficiency in a contact-engineered broadband a-IGZO phototransistor,” Advanced Functional Materials, 2200282, 2022. [LINK]
B. Liu, Y.-F. Chang, J. Li, X. Liu, L. A. Wang, D. Verma, H. Liang, H. Zhu, Y. Zhao, L.-J. Li, T.-H. Hou, C.-S. Lai, “Bi2O2Se-based true random number generator for security applications,“ ACS Nano, vol. 16, pp. 6847-6857, 2022. [LINK]
I.-T. Wang, C.-C. Chang, Y.-Y. Chen, Y.-S. Su, and T.-H. Hou, “Two‐dimensional materials for artificial synapses: toward a practical application,“ Neuromorphic Computing and Engineering, vol. 2, 012003, 2022. [LINK]
C.-J. Liu, Y. Wan, L.-J. Li, C.-P. Lin, T.-H. Hou, Z.-Y. Huang, and V. P.-H. Hu, “Two‐dimensional materials‐based static random‐access memory,” Advanced Materials, 2107894, 2022. [LINK]
C.-C. Chang, I.-T. Wang, H.-H. Huang, B. Hudec, M.-H. Wu, C.-C. Chang, P.-T. Liu, and T.-H. Hou, “Strategy of mitigating breakdown interference and yield loss in crossbar memory,” IEEE Trans. Elec. Dev., vol. 68, no. 12, pp. 6082-6086, Dec. 2021. [LINK]
M. Lanza, R. Waser, D. Ielmini, J. J. Yang, L. Goux, J. Sune, A. J. Kenyon, A. Mehonic, S. Spiga, V. Rana, S. Wiefels, S. Menzel, I. Valov, M. A. Villena, E. Miranda, X. Jing, F. Campabadal, M. Gonzalez, F. Aguirre, F. Palumbo, K. Zhu, J. B. Roldan, F. M. Puglisi, L. Larcher, T.-H. Hou, T. Prodromakis, Y. Yang, P. Huang, T. Wang, Y. Chai, K. L. Pey, N. Raghavan, S. Duenas, T. Wang, Q. Xia, and S. Pazos, “Standards for the characterization of endurance in resistive switching devices,” ACS Nano, vol. 15, pp. 17214−17231, Nov. 2021. [LINK]
B. Liu, Y. Zhao, D. Verma, L. A. Wang, H. Liang, H. Zhu, L.-J. Li, T.-H. Hou, and C.-S. Lai, “Bi2O2Se-based memristor-aided logic,” ACS Appl. Mater. Inter., vol. 13, no. 23, pp. 15391–15398, Mar. 2021. [LINK]
Conference
(頂尖會議) C.-Y. Cho, T.-Y. Chao, T.-Y. Lin, I-T. Wang, Y.-S. Chen, Y.-C. Ong, Y.-D. Lin, P.-C. Yeh, S.-S. Sheu, and T.-H. Hou, “Wake-up of ultrathin ferroelectric Hf0.5Zr0.5O2: The origin and physical modeling” International Electron Devices Meeting (IEDM) 2023, 24-2, San Francisco, CA, USA, Dec. 9-13, 2023. [LINK]
(頂尖會議) X.-R. Yu, C.-C. Hsieh, M.-H. Chuang, M.-Y. Chiu, T.-C. Sun, W.-Z. Geng, W.-H. Chang, Y.-J. Shih, W.-H. Lu, W.-C. Chang, Y.-C. Lin, Y.-C. Pai, C.-Y. Lai, C.-Y. Yang, Y. Dei, N.-C. Lin, H.-Y. Lu, M.-H. Chuang, W. C.-Y. Ma, C.-T. Wu, K.-H. Kao, D. D. Lu, Y.-J. Lee, G.-L. Luo, M.-H. Chiang, T. Maeda, W.-F. Wu, Y.-M. Li, T.-H. Hou, and Y.-H. Wang, “First demonstration of defect elimination for cryogenic Ge FinFET CMOS inverter showing steep subthreshold slope by using Ge-on-insulator structure” International Electron Devices Meeting (IEDM) 2023, 2-6, San Francisco, CA, USA, Dec. 9-13, 2023. [LINK]
(頂尖會議) E. Ambrosi, C.-H. Wu, M.-Y. Song, H.-Y Lee, K.-S. Li, C.-C. Lin, C.-F. Hsu, C.-C. Kuo, W. N. Chang, Y. J. Chen, C. H. Lin, J. M. Shieh, C. H. Shen, T. Y. S. Lee, T.-H. Hou, and X. Bao, “Low voltage (<1.8 V) and high endurance (>1M) 1-Selector/1-STT-MRAM with ultra-low (1 ppb) read disturb for high density embedded memory arrays,” International Electron Devices Meeting (IEDM) 2023, 21-5, San Francisco, CA, USA, Dec. 9-13, 2023. [LINK]
(頂尖會議) K.-S. Li, J.-M. Shieh, Y.-J. Chen, C.-L. Hsu, C.-H. Shen, T.-H. Hou, C.-P. Lin, C.-H. Lai, D. D. Tang, J. Y.-C. Sun, “First BEOL-compatible, 10 ns-fast, and durable 55 nm top-pSOT-MRAM with high TMR (>130%),” International Electron Devices Meeting (IEDM) 2023, 31-4, San Francisco, CA, USA, Dec. 9-13, 2023. [LINK]
(Keynote)(Invited) T.-H. Hou, “Toward practical applications of analog in-memory computing: from AI acceleration to combinatorial optimization,” the 6th International Conference on Memristive Materials, Devices & Systems (MEMRISYS) 2023, Torino, Italy, Nov. 5 – 9, 2023.
Hudec, C.-C. Chang, T.-H. Hou, “Probing degradation mechanisms of oxide analog memristors by a combination of thin film spectroscopy techniques,” the 6th International Conference on Memristive Materials, Devices & Systems (MEMRISYS) 2023, Torino, Italy, Nov. 5 – 9, 2023.
J. Chang, C.-I. Lu, W.-N. Chang, C.-C. Lin, and T.-H. Hou, “An investigation of the stability of thickness-scaled indium oxide and In-rich InGaZnO TFTs,” International Electron Devices and Materials Symposia (IEDMS) 2023, Kaohsiung City, Taiwan, Oct. 19–20, 2023. (Best Oral Paper Award)
(Invited) T.-H. Hou, “Intelligent memory in future high-performance computing,” International Taiwan-Japan Semiconductor Technology Symposium, Taipei, Taiwan, Sep. 7, 2023.
(頂尖會議) M. -H. Wu, M. -C. Hong, C. Shih, Y. -J. Chang, Y. -C. Hsin, S. -C. Chiu, K. -M. Chen, Y. -H. Su, C. -Y. Wang ,S. -Y. Yang, G. -L. Chen, H. -H. Lee, S. Z. Rahaman, I. -J. Wang, C. -Y. Shih, T. -C. Chang, J. -H. Wei, S. -S. Sheu, W. -C. Lo, S. -C. Chang, T. -H. Hou, “U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory,” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2023, pp. 1-2, doi: 10.23919/VLSITechnologyandCir57934.2023.10185336.
(頂尖會議) K.-Y. Hsiang, J.-Y. Lee, F.-S. Chang, Z.-F. Lou, Z.-X. Li, Z.-H. Li, J.-H. Chen, C.-W. Liu, T.-H. Hou, M.-H. Lee, “FeRAM Recovery up to 200 Periods with Accumulated Endurance 1012 Cycles and an Applicable Array Circuit toward Unlimited eNVM Operations,” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2023, pp. 1-2, doi: 10.23919/VLSITechnologyandCir57934.2023.10185274.
Y. -C. Guo, W. -T. Lin, T. -H. Hou and T. -S. Chang, “FPCIM: A Fully-Parallel Robust ReRAM CIM Processor for Edge AI Devices,” 2023 IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, 2023, pp. 1-5, doi: 10.1109/ISCAS46773.2023.10181402.
M.-C. Hong, Y.-H. Su, G.-L. Chen, Y.-C. Hsin, Y.-J. Chang, K.-M. Chen, S.-Y. Yang, I.-J. Wang, S. Z. Rahaman, H.-H. Lee, J.-H. Wei, S.-S. Sheu, W.-C. Lo, S.-C. Chang, T.-H. Hou, “Design of High-RA STT-MRAM for Future Energy-Efficient In-Memory Computing,” 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT), Hsinchu, Taiwan, 2023, pp. 1-2 [LINK]
(Invited) I-T. Wang, H.-H. Huang, C.-Y. Chiu, C.-Y. Cho, T.-Y. Lin, and T.-H. Hou, “Interface engineering toward future low-energy and scalable ferroelectric memory,” MRS spring meeting 2023, San Francisco, CA, USA, Apr. 10 – 14, 2023.
K.-Y. Hsiang, J.-Y. Lee, Z.-F. Lou, F.-S. Chang, Z.-X. Li, C. W. Liu, T.-H. Hou, P. S2 and M. H. Lee, “Cryogenic Endurance of Anti-ferroelectric and Ferroelectric Hf1-xZrxO2 for Quantum Computing Applications,” 2023 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 2023, pp. 1-4. [LINK]
Y. -H. Chen, I. -T. Wang, Y. -M. Zheng and T. -H. Hou, “Guideline of Device Optimization for Ferroelectric InGaZnO Transistor,” 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Seoul, Republic of Korea, 2023, pp. 1-3. [LINK]
(Invited)J.-H. Lee, C.-H. Chou, P.-J. Liao, Y.-K. Chang, H.-H. Huang, T.-Y. Lin, Y.-S. Liu, C.-H. Nien, D.-H. Hou, T.-H. Hou, and J. He, “Investigation of defect engineering toward prolonged endurance for HfZrO based ferroelectric device,” International Electron Devices Meeting (IEDM) 2022, San Francisco, CA, USA, Dec. 3-7, 2022.
H.-H. Huang, C.-Y. Cho, T.-Y. Lin, T.-S. Huang, M.-H. Wu, I-T. Wang, Y.-K. Chang, C.-H. Chou, P.-J. Liao, H.-Y. Yang, Y.-D. Lin, P.-C. Yeh, S.-S. Sheu, and T.-H. Hou, “Modeling fatigue-breakdown dilemma in ferroelectric Hf0.5Zr0.5O2 and optimized programming strategies,” International Electron Devices Meeting (IEDM) 2022, San Francisco, CA, USA, Dec. 3-6, 2022. [LINK]
Y.-D. Lin, P.-C. Yeh, J.-Y. Dai, J.-W. Su, H.-H. Huang, C.-Y. Cho, Y.-T. Tang, T.-H. Hou, S.-S. Sheu, W.-C. Lo, and S.-C. Chang, “Highly reliable, scalable, and high-yield HfZrOx FRAM by barrier layer engineering and post-metal annealing,” International Electron Devices Meeting (IEDM) 2022, San Francisco, CA, USA, Dec. 3-6, 2022. [LINK]
K.-Y. Hsiang, Y.-C. Chen, F.-S. Chang, C.-Y. Lin, C.-Y. Liao, Z.-F. Lou, J.-Y. Lee, W.-C. Ray, Z.-X. Li, C.-C. Wang, H.-C. Tseng, P.-H. Chen, J.-H. Tsai, T.-H. Hou, C. W. Liu, P.-T. Huang, P. Su, and M. H. Lee, “Novel opposite polarity cycling recovery (OPCR) of HfZrO2 antiferroelectric-RAM with an access scheme toward unlimited endurance,” International Electron Devices Meeting (IEDM) 2022, San Francisco, CA, USA, Dec. 3-6, 2022. [LINK]
M.-C. Hong, Y.-J. Chang, Y.-C. Hsin, L.-M. Liu, K.-M. Chen, Y.-H. Su, G.-L. Chen, S.-Y. Yang, I-J. Wang, SK Z. Rahaman, H.-H. Lee, S.-C. Chiu, C.-Y. Shih, C.-Y. Wang, F.-M. Chen, J.-H. Wei, S.-S. Sheu, W.-C. Lo, M.-T. Lin, C.-I Wu, and T.-H. Hou, ” A 4K−400K wide operating-temperature-range MRAM technology with ultrathin composite free layer and magnesium spacer,” Symposium on VLSI Technology and Circuits (VLSI) 2022, T11.4, Honolulu, HI, USA, Jun. 13-17, 2022. [LINK]
C. Liu, S.-T. Li, T.-L. Pan, C.-E. Ni, Y. Sung, C.-L. Hu, K.-Y. Chang, T.-H. Hou, T.-S. Chang, and S.-J. Jou, “An 1-bit by 1-bit high parallelism in-RRAM macro with co-training mechanism for DCNN applications,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2022, Hsinchu, Taiwan, Apr. 18–21, 2022. [LINK]
Z.-F. Lou, C.-Y. Liao, K.-Y. Hsiang, C.-Y. Lin, Y.-D. Lin, P.-C. Yeh, C.-Y. Wang, H.-Y. Yang, P.-J. Tzeng, T.-H. Hou, Y.-T. Tang, and M.-H. Lee, “Characterization of double HfZrO2 based FeFET toward low-voltage multi-level operation for high density nonvolatile memory,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2022, Hsinchu, Taiwan, Apr. 18–21, 2022. [LINK]
T.-S. Huang, P.-C. Yeh, H.-Y. Yang, Y.-D. Lin, P.-J. Tzeng, S.-S. Sheu, W.-C. Lo, C.-I. Wu, and T.-H. Hou, “Area scalable hafnium-zirconium-oxide ferroelectric capacitor using low-temperature back-end-of-line compatible 400℃ annealing,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2022, Hsinchu, Taiwan, Apr. 18–21, 2022. [LINK]
K.-Y. Hsiang, C.-Y. Liao, Y.-Y. Lin, Z.-F. Lou, C.-Y. Lin, J.-Y. Lee, F.-S. Chang, Z.-X. Li, H.-C. Tseng, C.-C. Wang, W.-C. Ray, T.-H. Hou, T.-C. Chen, C.-S. Chang, and M.-H. Lee, “Correlation between access polarization and high endurance (~ 1012 cycling) of ferroelectric and anti-ferroelectric HfZrO2,” International Reliability Physics Symposium (IRPS) 2022, P9, Dallas, TX, USA, Mar. 27-31, 2022. [LINK]
(Invited)T.-H. Hou, “In-memory computing for future AI acceleration,” The 27th Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, Taiwan, Jan. 17-20, 2022.
M.-C. Hong, L.-C. Cho, C.-S. Lin, Y.-H. Lin, P.-A. Chen, I-T. Wang, P.-J. Tzeng, S.-S. Sheu, W.-C. Lo, C.-I Wu, and T.-H. Hou, “In-memory annealing unit (IMAU): Energy-efficient (2000 TOPS/W) combinatorial optimizer for solving travelling salesman problem,” International Electron Devices Meeting (IEDM) 2021, pp. 470-473, San Francisco, CA, USA, Dec. 11-15, 2021. [LINK]
Y.-D. Lin, P.-C. Yeh, Y.-T. Tang, J.-W. Su, H.-Y. Yang, Y.-H. Chen, C.-P. Lin, P.-S. Yeh, J.-C. Chen, P.-J. Tzeng, M. –H. Lee, T.-H. Hou, S.-S. Sheu, W.-C. Lo, and C.-I Wu, “Improving edge dead domain and endurance in scaled HfZrOx FeRAM,” International Electron Devices Meeting (IEDM) 2021, pp. 135-137, San Francisco, CA, USA, Dec. 11-15, 2021. [LINK]
C.-Y. Liao, K.-Y. Hsiang, Z.-F. Luo, C.-Y. Lin, Y.-D. Lin, P.-C. Yeh, C.-Y. Wang, H.-Y. Yang, P.-J. Tzeng, Y.-T. Tang, T.-H. Hou, and M. H. Lee, “BEOL (Back End of Line) applicable ferroelectric HfZrO2 by PEALD with low temperature annealing, wake-up free, and synaptic application,” IEEE Semiconductor Interface Specialists Conference (SISC) 2021, San Diego, CA, Dec. 8-11, 2021.
C.-S. Lin, F.-C. Tsai, J.-W. Su, S.-H. Li, T.-S. Chang, S.-S. Sheu, W.-C. Lo, S.-C. Chang, C.-I. Wu, and T.-H. Hou, “A 48 Tops and 20943 TOPS/W 512kb computation-in-SRAM macro for highly reconfigurable ternary CNN acceleration,” IEEE Asian Solid-State Circuits Conference (ASSCC) 2021, 8.5, Busan, South Korea, Nov. 7–10, 2021. [LINK]
(Invited)T.-H. Hou, “Smart memory of the future,” 2021 Japan-Taiwan Advanced Materials and Semiconductor Technology Workshop, Hsinchu, Taiwan, Oct. 28, 2021.
(Invited)(Tutorial) T. H. Hou, ” Robust and reliable design for in-memory computing,” International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) 2021, Singapore, Sep. 14, 2021.
(Invited)C.-P. Lin, Y.-W. Kang, C.-P. Hsu, H.-H. Hsu, J.-H. Huang, R.-F. Chen, C.-T. Wu, Y.-J. Lee, and T.-H. Hou, “Monolithic 3D integration of 2D electronics based on two-dimensional solid-phase crystallization,” Symposium on VLSI Technology and Circuits (VLSI) 2021, TFS2-2, Kyoto, Japan, Jun. 13-19, 2021.
(Invited)T.-H. Hou, “Why is STT-MRAM a strong contender for efficient neuromorphic computing?,” 3rd International Memory Symposium, Hong Kong, May 26-29, 2021.
(Best Student Paper Award)Y.-H. Chu, H.-H. Huang, Y.-H. Chen, C.-H. Hsu, P.-J. Tzeng, S.-S. Sheu, W.-C. Lo, C.-I Wu, and T.-H. Hou, “Ultra-thin Hf0.5Zr0.5O2 ferroelectric tunnel junction with high current density,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2021, pp. 147-148, Hsinchu, Taiwan, Apr. 19–22, 2021. [LINK]
(Invited)T.-H. Hou, “Toward energy-efficient, cost-effective, and variation-aware in-memory computing for deep learning acceleration,” Electron Devices Technology and Manufacturing Conference (EDTM), Chengdu, China, Arp.8-11, 2021.
(Invited)T.-H. Hou, “Cross-layer optimization strategy for energy-efficient and variation-aware in-memory computing,” International Symposium on Quality Electronic Design (ISQED), virtual, CA, USA, Apr. 7-9, 2021.
T.-L. Pan, S.-T. Li, C. Liu, T.-H. Hou, S.-J. Jou and T.-S. Chang, “Robust model mapping optimization for non-ideal computing in-memory,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2021, Hsinchu, Taiwan, Apr. 19–22, 2021. [LINK]
US Patent
T.-H. Hou, C.-C. Chang, “Device and method for operating the same,” US Patent 11,494,619, Nov. 8 , 2022. [LINK]
F.-C. Tsai, H.-Y. Lee, C.-S. Lin, J.-W. Su, T.-H. Hou, “Computation operator in memory and operation method thereof,” US Patent 11,145,356, Oct. 12, 2021. [LINK]
T.-H. Hou, S.-C. Pan, and P.-S. Liu, “Impact ionization semiconductor device and manufacturing method thereof,” US Patent 11,031,510, Jun 8, 2021. [LINK]
T.-H. Hou, C.-C. Chang, and J.-C. Liu, “Neural network processing system,” US Patent 10,902,317, Jan 26, 2021. [LINK]
