L. Gao, I.-T. Wang, P.-Y. Chen, S. Vrudhula, J.-S. Seo, Y. Cao, T.-H. Hou, and S. Yu, ‘Fully parallel write/read in resistive synaptic array for accelerating on-chip learning,’ Nanotechnology, vol. 26, 455204, Oct. 2015. [LINK]
J. -C. Liu, C. -W. Hsu, I. -T. Wang and T. -H. Hou, “Categorization of Multilevel-Cell Storage-Class Memory: An RRAM Example,” in IEEE Transactions on Electron Devices, vol. 62, no. 8, pp. 2510-2516, Aug. 2015 [LINK]
Y.-F. Wang, Y.-C. Lin, I.-T. Wang, T.-P. Lin, and T. H. Hou, ‘Characterization and modeling of nonfilamentary Ta/TaOx/TiO2/Ti analog synaptic device,’ Scientific Reports, vol. 5, 10150, May 2015. [LINK]
L. Zhao, H.-Y. Chen, S.-C. Wu, Z. Jiang, S. Yu, T. H. Hou, H.-S. Philip Wong, and Y. Nishi, ‘Multi-level control of conductive nano-filament evolution in HfO2 ReRAM by pulse-train operations,’ Nanoscale, vol. 6, pp. 5698-5702, Jun. 2014. [LINK]
C. W. Hsu, Y. F. Wang, C. C. Wan, I. T. Wang, C. T. Chou, W. L. Lai, Y. J. Lee, and T. H. Hou, ‘Homogeneous barrier modulation of TaOx/TiO2 bilayer for ultra-high endurance three-dimensional storage-class memory,’ Nanotechnology, vol. 25, 165202, Mar. 2014. [LINK]
W. C. Luo, J. C. Liu, Y. C. Lin, C. L. Lo, J. J. Huang, K. L. Lin, and T. H. Hou, ‘Statistical model and rapid prediction of RRAM SET speed–disturb dilemma,’ IEEE Trans. Elec. Dev., vol. 60, no. 11, pp. 3760-3766, Nov. 2013. [LINK]
S. C. Wu, H. T. Feng, M. J. Yu, I. T. Wang, and T. H. Hou, “Flexible three-bit-per-cell resistive-switching memory using a-IGZO TFTs,” IEEE Electron Device Letters, vol. 34, no. 10, pp. 1265-1267, Oct. 2013. [LINK]
W. C. Luo, T. H. Hou, K. L. Lin, Y. J. Lee, and T. F. Lei, ‘Reversible transition of resistive switching induced by oxygen-vacancy and metal filaments in HfO2,’ Solid-State Electron., vol. 89, pp. 167–170, Aug. 2013. [LINK]
C. W. Hsu, T. H. Hou, M. C. Chen, I. T. Wang, and C. L. Lo, “Bipolar Ni/TiO2/HfO2/Ni RRAM with multilevel states and self-rectifying characteristics,” IEEE Electron Device Letters, vol. 34, no. 7, pp. 885-887, Jul. 2013. [LINK]
K. L. Lin, T. H. Hou, Y. J. Lee, J. W. Chang, J. H. Lin, J. Shieh, C. T. Chou, T. F. Lei, W. H. Chang, W. Y. Jang, and C. H. Lin, ‘Switching mode and mechanism in binary oxide RRAM using Ni electrode,’ Jpn. J. Appl. Phys., vol. 52, 031801, Feb. 2013. [LINK]
C. L. Lo, T. H. Hou, M. C. Chen, and J. J. Huang, “Dependence of read margin on pull-up schemes in high-density one selector-one resistor (1S1R) crossbar array,” IEEE Trans. Elec. Dev., vol. 60, no. 1, pp.420-426, Jan. 2013. [LINK]
S. C. Wu, T. H. Hou, S. H. Chuang, H. C. Chou, T. S. Chao, and T. F. Lei, ‘Polycrystalline silicon thin-film transistor with nickel-titanium oxide by sol-gel spin-coating and nitrogen implantation,’ Solid-State Electron., vol. 78, pp. 11–16, Dec. 2012. [LINK]
W. C. Luo, K. L. Lin, J. J. Huang, C. L. Lee, and T. H. Hou, “Rapid prediction of RRAM RESET-state disturb by ramped voltage stress,” IEEE Electron Device Letters, vol. 33, no. 4, pp.597-599, Apr. 2012. [LINK]
J. J. Huang, T. H. Hou, C. W. Hsu, Y. M. Tseng, W. H. Chang, W. Y. Jang, and C. H. Lin, “Flexible one diode-one resistor crossbar resistive-switching memory,” Jpn. J. Appl. Phys., vol. 51, 04DD09, Apr. 2012. [LINK]
J. T. Shaw, S. Q. Xu, S. Rajwade, T. H. Hou, and E. C. Kan “Redox molecules for resonant tunneling barrier in nonvolatile memory,” IEEE Trans. Elec. Dev., vol. 58, no. 3, pp.826-834, Mar. 2012. [LINK]
M. J. Yu, Y. H. Yeh, C. C. Cheng, C. Y. Lin, G. T. Ho, B. C. Lai, C. M. Leu, T. H. Hou, and Y. J. Chan, “Amorphous InGaZnO thin-film transistors compatible with roll-to-roll fabrication at room temperature,” IEEE Electron Device Letters, vol. 33, no. 1, pp. 47-49, Jan. 2012. [LINK]
J. Lee, J. J. Cha, S. Barron, D. A. Muller, R. B. van Doverc, E. K. Amponsaha, T. H. Hou, H. Raza, and E. C. Kan, “Stackable nonvolatile memory with ultra thin polysilicon film and low-leakage (Ti, Dy)xOy for low processing temperature and low operating voltages,” Microelectronic Engineering, vol. 88, no. 12, pp. 3462-3465, Dec. 2011. [LINK]
S. C. Wu, C. Lo, and T. H. Hou, “Novel two-bit-per-cell resistive-switching memory for low-cost embedded applications,” IEEE Electron Device Letters, vol. 32, no. 12, pp. 1662-1664, Dec. 2011. [LINK]
J. J. Huang, Y. M. Tseng, C. W. Hsu, and T. H. Hou, “Bipolar nonlinear Ni/TiO2/Ni selector for 1S1R crossbar array applications,” IEEE Electron Device Letters, vol. 32, no. 10, pp.1427-1429, Oct. 2011. [LINK]
K. L. Lin, T. H. Hou, J. Shieh, J. H. Lin, C. T. Chou, and Y. J. Lee, “Electrode dependence of filament formation in HfO2 resistive-switching memory,” J. Appl. Phys., vol. 109, no 8, 084104, Apr. 2011. [LINK]
T. H. Hou, K. L. Lin, J. Shieh, J. H. Lin, C. T. Chou, and Y. J. Lee, “Evolution of RESET current and filament morphology in low-power HfO2 unipolar resistive switching memory, “ Appl. Phys. Lett., vol. 98, no. 10, 103511, Mar. 2011 (Also appeared in Virtual Journal of Nanoscale Science & Technology). [LINK]
J. Shaw, Y. W. Zhong, K. Hughes, T. H. Hou, H. Raza, S. Rajwade, J. Bellfy, J. R. Engstrom, H. D. Abruña, and E. C. Kan “Integration of self-assembled redox molecules in flash memories,” IEEE Trans. Elec. Dev., vol. 58, no. 3, pp.826-834, Mar. 2011. [LINK]
S. H. Chuang, M. L. Hsieh, S. C. Wu, H. C. Lin, T. S. Chao, and T. H. Hou, “Fabrication and characterization of high-k dielectric nickel titanate thin films using a modified sol–gel method,” J. Am. Ceram. Soc., vol. 94, no. 1, pp. 250-254, Jan. 2011. [LINK]
Book Chapter
T. H. Hou. Metal-oxide resistive-switching RAM technology. McGraw-Hill 2011 Yearbook of Science and Technology, ISBN 9780071763714.
Conference
Y.-J. Lee, F.-J. Hou, S.-S. Chuang, F.-K. Hsueh, K.-H. Kao, P.-J. Sung, W.-Y. Yuan, Y.-C. Lu, K.-L. Lin, C.-T. Wu, J.-Y. Yao, H.-C. Chen, Henry J. H. Chen, T.-S. Chao, T.-Y. Tseng, W.-F. Wu, T.-H. Hou, W. -K. Yeh, “Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology,” International Electron Devices Meeting (IEDM) 2015, pp. 382-385, Washington, DC, USA, Dec. 7-9, 2015. (2015 IEDM Highlighted Paper)
C.-T. Lin, C.-P. Lin, P.-S. Liu, L.-J. Li, and T.-H. Hou, “Improving contact resistance of 2D MoS2 transistor using H2 plasma treatment,” International Electron Devices and Materials Symposia (IEDMS) 2015, Tainan, Taiwan, Nov. 19–20, 2015.
L.-W. Chiu, I-T. Wang, and T.-H. Hou, “Influence of input strength on retention characteristics in Ta/TaOx/TiO2/Ti synaptic device,” International Electron Devices and Materials Symposia (IEDMS) 2015, Tainan, Taiwan, Nov. 19–20, 2015.
P.-Y. Chen, B. Lin, I-T. Wang, T.-H. Hou, J. Ye, S. Vrudhula, J.-S. Seo, Y. Cao, and S. Yu, ‘Mitigating effects of non-ideal synaptic device characteristics for on-chip learning,’ International Conference On Computer Aided Design (ICCAD) 2015, pp. 194-199, Austin, TX, USA, Nov. 2-6, 2015.
B. Hudec, I-T. Wang, W.-L. Lai, C.-C. Zhang, T.-H. Hou, P. Jančovič, K. Fröhlich, and M. Micušík, ‘Interface engineered HfO2-based 3D vertical resistive random access memory with forming-free operation,’ International Conference on Solid State Devices and Materials (SSDM) 2015, Sapporo, Japan, Sep. 27-30, 2015.
C.-P. Lin, P.-S. Liu, L.-S. Lyu, M.-Y. Li, C.-C. Cheng, T.-H. Lee, W.-H. Chang, L.-J. Li, and T.-H. Hou, ‘N-type doping effect of transferred MoS2 and WSe2 monolayer,’ International Conference on Solid State Devices and Materials (SSDM) 2015, Sapporo, Japan, Sep. 27-30, 2015.
K. Fröhlich, P. Jančovič, J. Dérer, E. Dobročka, B. Hudec, P. Calka, C. Walczyk, G. Niu, T. Schroeder, I-T. Wang, C. W. Hsu, and T.-H. Hou ‘Atomic layer deposited HfO2 films for next generation resistive switching memory,’ International Baltic Conference on Atomic Layer Deposition 2015, Tartu, Estonia, Sep. 28–29, 2015.
(Invited paper) T. H. Hou, ‘3D RRAM-based synaptic network with low programming energy,’ 5th Stanford-imec International RRAM Workshop, Leuven, Belgium, September 24–25, 2015.
Y.-H. Lai and T.-H. Hou, ‘Oxygen plasma-treated ALD ZnO thin film transistors,’ International Display Manufacturing Conference (IDMC) 2015, Taipei, Taiwan, Aug. 25-28, 2015.
C.-P. Lin, L.-S. Lyu, C.-T. Lin, P.-S. Liu, W.-H. Chang, L.-J. Li, and T.-H. Hou, ‘Grain size effect of monolayer MoS2 transistors characterized by second harmonic generation mapping,’ International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) 2015, Hsinchu, Taiwan, Jun. 29–Jul. 2, 2015.
R. Lo, P.-Y. Du, T.-H. Hsu, C.-J. Wu, J.-Y. Guo, C.-M. Cheng, H.-T. Lue, Y.-H. Shih, T.-H. Hou, K.-Y. Hsieh, and C.-Y. Lu, “A Study of blocking and tunnel oxide engineering on double-trapping (DT) BE-SONOS performance” 7th International Memory Workshop (IMW), Monterey, CA, May 17–20, 2015.
T. Chou, J.-C. Liu, L.-W. Chiu, I.-T. Wang, C.-M. Tsai, and T.-H. Hou, ‘Neuromorphic pattern learning using HBM electronic synapse with excitatory and inhibitory plasticity,’ International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2015, Hsinchu, Taiwan, Apr. 27–29, 2015.
(Invited paper) T. H. Hou, ‘3D RRAM technology for electronic synapses applications,’ China Semiconductor Technology International Conference (CSTIC 2015), Shanghai, China, March 15–16, 2015.
I.-T. Wang, Y.-C. Lin, Y.-F. Wang, C.-W. Hsu, and T.-H. Hou, ‘3D synaptic architecture with ultralow sub-10 fJ energy per spike for neuromorphic computation,’ International Electron Devices Meeting (IEDM) 2014, pp. 665-668, San Francisco, CA, USA, Dec. 15-17, 2014.
P.-S. Liu, C.-H. Chen, W.-T. Hsu, C.-P. Lin, T.-P. Lin, L.-J. Chi, C.-Y. Chang, S.-C. Wu, W.-H. Chang, L.-J. Li and T.-H. Hou, ‘Fast visible-light phototransistor using CVD-synthesized large-area bilayer WSe2,’ International Electron Devices Meeting (IEDM) 2014, pp. 132-135, San Francisco, CA, USA, Dec. 15-17, 2014.
T.-P. Lin, Y.-F. Wang, and T.-H. Hou, “Simulation of nonpolar resistive-switching memory,” International Electron Devices and Materials Symposia (IEDMS) 2014, Hualien, Taiwan, Nov. 20 – Nov. 21, 2014.
L.-J. Chi, Y.-H. Chang, and T.-H. Hou, “Demonstrating high-performance a-InGaZnO inverter at room-temperature for BEOL applications,” International Electron Devices and Materials Symposia (IEDMS) 2014, Hualien, Taiwan, Nov. 20 – Nov. 21, 2014.
C.-P. Lin, P.-S. Liu, C.-Y. Chang, S.-C. Wu, L.-J. Li, and T.-H. Hou, “Effect of HfO2 gate dielectrics on WSe2 transistors,” International Electron Devices and Materials Symposia (IEDMS) 2014, Hualien, Taiwan, Nov. 20 – Nov. 21, 2014.
W.-L. Lai, C.-T. Chou, C.-W. Hsu, T.-P. Lin, B. Hudec, and T.-H. Hou, “Crossbar array of TaOx/TiO¬2 bilayer RRAM,” International Electron Devices and Materials Symposia (IEDMS) 2014, Hualien, Taiwan, Nov. 20 – Nov. 21, 2014.
C.-C. Chang, J.-C. Liu, and T.-H. Hou, “RRAM crossbar array analysis with line resistance,” International Electron Devices and Materials Symposia (IEDMS) 2014, Hualien, Taiwan, Nov. 20 – Nov. 21, 2014.
(Invited paper) T. H. Hou, ‘Statistical study and rapid prediction methodology of RRAM SET speed-disturb dilemma,’ 2014 Taiwan ESD and Reliability Conference (2014 T-ESDA), Hsinchu, Taiwan, Nov. 11–13, 2014.
W.-L. Lai, C.-T. Chou, C.-W. Hsu, J.-C. Liu, B. Hudec, C.-H. Ho, W.-Y. Jang, C.-H. Lin, and T. H. Hou, ‘Interface engineering in homogeneous barrier modulation RRAM for 3D vertical memory applications,’ International Conference on Solid State Devices and Materials (SSDM) 2014, Tsukuba, Japan, Sep. 8-11, 2014.
J.-C. Liu, I.-T. Wang, C.-W. Hsu, W.-C. Luo, and T.-H. Hou, ‘Investigating MLC variation of filamentary and non-filamentary RRAM,’ International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2014, Hsinchu, Taiwan, Apr. 28–30, 2014.
L. Zhao, H.-Y. Chen, S.-C. Wu, Z. Jiang, S. Yu, T.-H. Hou, H.-S. P. Wong, and Y. Nishi, ‘Improved multi-level control of RRAM using pulse-train programming,’ International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2014, Hsinchu, Taiwan, Apr. 28–30, 2014. (Best Student Paper Award)
(Invited paper) T. H. Hou, ‘Emerging RRAM for 3D storage-class memory,’ China Semiconductor Technology International Conference (CSTIC 2014), Shanghai, China, March 16–17, 2014.
C. W. Hsu, C. C. Wan, I. T. Wang, M. C. Chen, C. L. Lo, Y. J. Lee, W. Y. Jang, C. H. Lin, and T. H. Hou, ‘3D vertical TaOx/TiO2 RRAM with over 103 self-rectifying ratio and sub-A operating current,’ International Electron Devices Meeting (IEDM) 2013, pp. 264-268, Washington, DC, USA, Dec. 9-11, 2013.
Y. Deng, H.-Y. Chen, B. Gao, S. Yu, S.-C. Wu, L. Zhao, B. Chen, Z. Jiang, T.-H. Hou, Y. Nishi, J. Kang, and H.-S. P. Wong, ‘Design and optimization methodology for 3D RRAM arrays,’ International Electron Devices Meeting (IEDM) 2013, pp. 629-632, Washington, DC, USA, Dec. 9-11, 2013.
(Invited paper) T. H. Hou, C. W. Hsu, and I. T. Wang, ‘Advance of 3D-stackable binary-oxide ReRAM for storage-class memory applications,’ AVS 60th International Symposium and Exhibition (AVS 2013), Long Beach, California, USA, October 28 – 30, 2013.
(Invited paper) T. H. Hou, S. C. Wu, M. J. Yu, P. S. Liu, and L. J. Chi, ‘Low-cost embedded RRAM technology for system-on-plastic integration using a-IGZO TFTs,’ International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD ’13), Kyoto, Japan, July 2 – 5, 2013.
C. W. Hsu, I. T. Wang, C. L. Lo, M. C. Chiang, W. Y. Jang, C. H. Lin and T. H. Hou, ‘Self-rectifying bipolar TaOx/TiOx RRAM with superior endurance over 1012 cycles for 3D high-density storage-class memory,’ Symposium on VLSI Technology 2013, pp. 166-167, Kyoto, Japan, Jun. 11-13, 2013.
P. S. Liu, I. T. Wang, S. C. Wu and T. H. Hou, ‘Characteristics of bipolar Ta/TaOx/Pt resistive-switching memory,’ Symposium on Nano Device Technology (SNDT) 2013, Hsinchu, Taiwan, Apr. 25-26, 2013.
C. T. Chou, I. T. Wang, C. W. Hsu, and T. H. Hou, ‘Mechanism of RRAM retention failure by temperature acceleration,’ Symposium on Nano Device Technology (SNDT) 2013, Hsinchu, Taiwan, Apr. 25-26, 2013.
C. L. Lo, M. C. Chen, J. J. Huang, and T. H. Hou, ‘On the potential of CRS, 1D1R, and 1S1R crossbar RRAM for storage-class memory,’ International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2013, Hsinchu, Taiwan, Apr. 22–24, 2013.
(Invited paper) T. H. Hou, S. C. Wu, M. J. Yu, and C. Lo, ‘Logic/RRAM hybrid thin-film transistor technology,’ Symposium on Nano Device Technology (SNDT) 2013, Hsinchu, Taiwan, Apr. 25-26, 2013.
S. C. Wu, H. T. Feng, M. J. Yu, I. T. Wang, and T. H. Hou, ‘Multi-bit-per-cell a-IGZO TFT resistive-switching memory for system-on-plastic applications,’ International Electron Devices Meeting (IEDM) 2012, pp. 100-103, San Francisco, CA, USA, Dec. 10-12, 2012.
W. C. Luo, J. C. Liu, H. T. Feng, Y. C. Lin, J. J. Huang, K. L. Lin, and T. H. Hou, ‘RRAM SET speed-disturb dilemma and rapid statistical prediction methodology,’ International Electron Devices Meeting (IEDM) 2012, pp. 215-218, San Francisco, CA, USA, Dec. 10-12, 2012.
C. W. Hsu, C. L. Lo, I. T. Wang, and T. H. Hou, ‘High-density 1S1R flexible bipolar resistive-switching memory,’ International Conference on Solid State Devices and Materials (SSDM) 2012, Kyoto, Japan, Sep. 25-27, 2012.
I. T. Wang, C. W. Hsu, and T. H. Hou, ‘Stable rectification and self-compliance resistive switching in Fe/TiO2/Pt MIM diode,’ Symposium on Nano Device Technology (SNDT) 2012, Hsinchu, Taiwan, Apr. 26-27, 2012.
S. C. Wu, C. Lo, and T. H. Hou, ‘Logic/resistive-switching hybrid transistor for two-bit-per-cell storage,’ International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 2012, Hsinchu, Taiwan, Apr. 23–25, 2012.
J. J. Huang, Y. M. Tseng, W. C. Luo, C. W. Hsu, and T. H. Hou, “One selector-one resistor (1S1R) crossbar array for high-density flexible memory applications,” International Electron Devices Meeting (IEDM) 2011, pp. 733-736, Washington, DC, USA, Dec. 5-7, 2011.
K. L. Lin, T. H. Hou, Y. J. Lee, J. H. Lin, J. W. Chang, J. Shieh, C. T. Chou, W. H. Chang, W. Y. Jang, and C. H. Lin, “Low-IRESET unipolar HfO2 RRAM and tunable resistive-switching mode via interface engineering,” International Semiconductor Device Research Symposium (ISDRS), College Park, MA, USA, December 9-11, 2011.
S. C. Wu, T. H. Hou, S. H. Chuang, H. C. Chou, T. S. Chao, and T. F. Lei, “Polycrystalline silicon thin-film transistor with nickel-titanium oxide by sol-gel spin-coating and nitrogen implantation,” International Semiconductor Device Research Symposium (ISDRS), College Park, MA, USA, December 9-11, 2011.
C. L. Lo, J. J. Huang, Y. M. Tseng, and T. H. Hou, “Read margin analysis on 1S1R crossbar RRAM — a study of numerical circuit simulation”, International Electron Devices and Materials Symposia (IEDMS) 2011, Nov. 17 – Nov. 18, 2011.
W. C. Huang, W. C. Luo, and T. H. Hou, “Fully CMOS-compatible chemoreceptive neuron MOS (CυMOS) transistor for fluid sensing”, International Electron Devices and Materials Symposia (IEDMS) 2011, Nov. 17 – Nov. 18, 2011.
C. W. Hsu, J. J. Huang, Y. M. Tseng, T. H. Hou, W. H. Chang, W. Y. Jang, and C. H. Lin, “Flexible one diode-one resistor crossbar resistive-switching memory,” International Conference on Solid State Devices and Materials (SSDM) 2011, Nagoya, Japan, Sep. 28-30, 2011.
K. L. Lin, Y. M. Tseng, J. H. Lin, J. Shieh, Y. J. Lee, T. H. Hou, and T. F. Lei, “High- performance Ni/SiO2/Si programmable metallization cell,” IEEE International NanoElectronics. Conference (INEC) 2011, Taoyuan, Taiwan, Jun. 21–24, 2011.
K. L. Lin, T. H. Hou, J. Shieh, J. H. Lin, C. T. Chou, and Y. J. Lee, “Comprehensive study on filament morphology in low-power unipolar Ni/HfO2/Si RRAM,” Symposium on Nano Device Technology (SNDT) 2011, Hsinchu, Taiwan, Apr. 22-23, 2011.
S. J. Fu, S. C. Wu, and T. H. Hou, “Aluminum-doped zinc oxide thin-film transistors with high- gate dielectrics,” Symposium on Nano Device Technology (SNDT) 2011, Hsinchu, Taiwan, Apr. 22-23, 2011.
US Patent
T. H. Hou, C. W. Hsu, and I. Ting Wang, ‘Self-rectifying RRAM cell structure and 3D crossbar array architecture thereof’, US Patent 9,059,391, June 16, 2015.
T. H. Hou and S. C. Wu, “Multi-bit resistive switching memory cell and array”, US Patent US 8,687,432, Apr. 1, 2014.
E. C. Kan and T. H. Hou, “Nonvolatile memory and methods for manufacturing the same with molecule-engineered tunneling barriers”, US Patent 8,542,540, Sep. 24, 2013.
