C. Lee, T. H. Hou, and E. C. Kan, 2005, Dec., “Nonvolatile memory with a metal nanocrystal/nitride heterogeneous floating gate,” IEEE Trans. Elec. Dev., vol. 52, no. 12, pp. 2697-2702, Dec. 2005. [LINK]
C. Lee, U. Ganguly, V. Narayanan, T. H. Hou and E. C. Kan, 2005, Dec., “Asymmetric electric field enhancement in nanocrystal memories,” IEEE Electron Device Letters, vol. 26, no. 12, pp. 879-881, Dec. 2005. [LINK]
C. W. Yang, Y. K. Fang, S. F. Chen, C. S. Lin, C. Y. Lin, W. D. Wang, T. H. Chou, P. J. Lin, M. F. Wang, T. H. Hou, L. G. Yao, S. C. Chen and M. S. Liang, “Reliability studies of Hf-doped and NH3-nitrided gate dielectric for advanced CMOS application,” IEE Proc.-Circuits Devices System, vol. 152, no. 5, pp. 407-410, Oct. 2005. [LINK]
C. M. Sparks, M. R. Beebe, J. Bennett, B. Foran, C. Gondran and A. Hou, “Characterization of high-k gate dielectric and metal gate electrode semiconductor samples with a total reflection X-ray fluorescence spectrometer,” Spectrochimica Acta. Part B, Atomic Spectroscopy, vol. 59, no. 8, pp. 1227-1234, Jul. 2004. [LINK]
J. J. Peterson, C. D. Young, J. Barnett, S. Gopalan, J. Gutt, C. H. Lee, H. J. Li, T. H. Hou, Y. Kim, C. Lim, N. Chaudhary, N. Moumen, B. H. Lee, G. Bersuker, G. A. Brown, P. M. Zeitzoff, M. I. Gardner, R. W. Murto, and H. R. Huff, “Subnanometer scaling of HfO2/metal electrode gate stacks,” Electrochem. Solid-State Lett., vol. 7, no. 8, G164-G167, Jun. 2004.
H.R. Huff, A. Hou, C. Lim, Y. Kim, J. Barnett, G. Bersuker, G.A. Brown, C. D.Young, P.M. Zeitzoff, J. Gutt, P. Lysaght, M.I. Gardner and R.W. Murto, “High-k gate stacks for planar, scaled CMOS integrated circuits,” Microelectronic Engineering, vol. 69, pp.152-167, Sep. 2003. [LINK]
C. W. Yang, Y. K. Fang, C. H. Chen, S. F. Chen, C. Y. Lin, C. S. Lin, M. F. Wang, Y. M. Lin, T. H. Hou, C. H. Chen, L. G. Yao, S. C. Chen, and M. S. Liang, “Effect of polycrystalline-silicon gate types on the opposite flatband voltage shift in n-type and p-type metal-oxide-semiconductor field-effect transistors for high-k-HfO2 dielectric,” Appl. Phys. Lett., vol. 83, no. 2, pp. 308 – 310, Jul 2003. [LINK]
C.-W. Yang, Y.-K. Fang, S.-F. Chen, M.-F. Wang, T.-H. Hou, Y.-M. Lin, L.-G. Yao, S.-C. Chen, and M.-S. Liang, “HfO2/HfSixOy high-K gate stack with very low leakage current for low-power poly-Si gated CMOS application,” Electron. Lett., vol. 39, no. 8, pp. 692-694, Apr. 2003. [LINK]
C.-W. Yang, Y.-K. Fang, S.-F. Chen, C.-Y. Lin, M.-F. Wang, Y.-M. Lin, T.-H. Hou, L.-G. Yao, S.-C. Chen, and M.-S. Liang, “Effective improvement of high-k Hf-silicate/silicon interface with thermal nitridation,” Electron. Lett., vol. 39, no. 5, pp.421–422, Mar. 2003. [LINK]
A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, H. E. Maes, and U. Schwalke, “Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics,” IEEE Electron Device Letters, vol.24, no.2, pp. 87-89, Feb. 2003. [LINK]
J. Bennett, C. Gondran, C. Sparks, P.Y. Hung, A. Hou, “SIMS depth profiling of advanced gate dielectric materials,” Appl. Surface Science, vol. 203-204, pp. 409-417, Jan. 2003. [LINK]
C.-W. Yang, Y.-K. Fang, C.-H. Chen, W.-D. Wang, T.-Y. Lin M.-F. Wang, T.-H. Hou, J.-Y. Cheng, L.-G. Yao, S.-C. Chen, C.-H. Yu, and M.-S. Liang, “Dramatic reduction of gate leakage current in 1.61 nm HfO2 high-k dielectric poly-silicon gate with Al2O3 capping layer,” Electron. Lett., vol. 38, no. 20, pp. 1223–1225, Sep. 2002. [LINK]
C. H. Chen, Y. K. Fang, C. W. Yang, S. F. Ting, Y. S. Tsai, C. N. Chang, T. H. Hou, M. F. Wang, M. C. Yu, C. L. Lin, S. C. Chen, C. H. Yu and M. S. Liang, “Improved current drivability and poly-gate depletion of submicron PMOSFET with poly-SiGe gate and ultra-thin nitride gate dielectric,” Solid-State Electronics, vol. 46, no. 4, pp. 597-599, Apr. 2002. [LINK]
C.H. Chen, Y.K. Fang, C.W. Yang, S.F. Ting, Y.S. Tsair, M.F. Wang, T. H. Hou, M.C. Yu, S.C. Chen, S. M. Jang, D.C.H. Yu and M.S. Liang, “To optimize electrical properties of the ultrathin (1.6 nm) nitride/oxide gate stacks with bottom oxide materials and post deposition treatment,” IEEE Trans. of Electron Device, vol. 48, no.12, pp.2769-2776, Dec. 2001. [LINK]
C.H. Chen, Y.K. Fang, C.W. Yang, S.F. Ting, Y.S. Tsair, T. H. Hou, M.F. Wang, M.C. Yu, S.C. Chen, S. M. Jang, D.C.H. Yu and M.S. Liang, “Thermally-enhanced remote plasma nitrided ultrathin (1.65 nm) gate oxide with excellent performances in reduction of leakage current and boron diffusion,” IEEE Electron Device Letters, vol.22, no.8, pp.378-380, Aug 2001. [LINK]
T. H. Hou, T. F. Lei, and T. S. Chao, “Improvement of junction leakage of nickel silicided junction by Ti-capping layer,” IEEE Electron Device Letters, vol. 20, no. 11, p.572, 1999. [LINK]
Conference
C. Lee, T. H. Hou, and E. C. Kan, 2005, “Metal nanocrystal/nitride heterogeneous-stack floating gate memory,” 63nd Device Research Conference, pp. 97-98, Santa Babara, CA, USA, Jun. 20-22, 2005.
W. H. Wu, M. F. Wang, T. H. Hou, L. G. Yao, Y. Jin. S. C. Chen, M. S. Liang, and M. C, Chen, “Effects of base oxide thickness in HfSiO/SiO2 high-k gate stacks,” 11th IEEE Int. Symposium on the physical and failure analysis of integrated circuits, pp. 25-28, Hsinchu, Taiwan, Jul. 5-8, 2004.
C. H. Chen, T. L. Lee, T. H. Hou, C. L. Chen, C. C. Chen, J. W. Hsu, K. L. Cheng, , Y.H. Chiu., H. J. Tao, Y. Jin, C. H. Diaz, S. C. Chen, and, M.-S. Liang, “Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application,” Symposium on VLSI Technology, pp. 56-57, Honolulu, HI, USA, Jun. 15-17, 2004.
M. F. Wang, T. H. Hou, K. L. Mai, P. S. Lim, L. G. Yao, Y. Jin, S. C. Chen and M. S. Liang, “Electrical performance improvement in SiO2/HfSiO high-k gate stack for advanced low power device application,” IEEE Int. Conference on Integrated Circuit Design and Technology, pp. 283-286, Austin, TX, USA, May 17-20, 2004.
T. H. Hou, M. F. Wang, K. L. Mai, Y. M. Lin, M. H. Yang, L. G. Yao, Y. Jin, S. C. Chen, and M. S. Liang, “Direct determination of interface and bulk traps in stacked HfO2 dielectrics using charge pumping method,” International. Reliability Physics Symposium (IRPS), pp. 581-582, Phoenix, AZ, USA, Apr. 25-29, 2004.
H.C. Wang, S. J. Chen; M. F. Wang, P. Y. Tsai, C. W. Tsai, T. W. Wang, S. M. Ting, T. H. Hou, P. S. Lim, H. J. Lin, Y. Jin, H. J. Tao, S. C. Chen, C.H. Diaz, M.-S Liang, and C. Hu; “Low power device technology with SiGe channel, HfSiON, and poly-Si gate,” International Electron Devices Meeting, pp. 161-164, San Francisco, CA, USA, Dec. 13-15, 2003.
C. D. Young, A. Kerber, T. H. Hou, E. Cartier, G. A. Brown, G. Bersuker, “Charge trapping and electron mobility degradation in MOCVD hafnium silicate gate dielectric stack structures,” 204th ECS meeting, Orlando, FL, USA, Oct. 12-16, 2003.
T. H. Hou, J. Gutt, C. Lim, S. Marcus, C. Pomarede, M. Gardner, R. Murto, and H. R. Huff, “Improved scalability of high-k gate dielectrics by using Hf-Aluminates,” 202nd ECS meeting, Salt Lake City, UT, USA, Oct. 20-24, 2002.
C. Lim, Y. Kim, A. Hou, J. Gutt, S. Marcus, C. Pomarede, L. Chen, G. Bease, J. Tamim, N. Chaudhary, G. Bersuker, J. Barnett, C. Young, P. Zeitzoff, G. Brown, M. Gardner, R. Murto, and H. Huff, “Effect of deposition sequence and plasma treatment on ALCVD HfO2 n-MOSFET properties,” 202nd ECS meeting, Salt Lake City, UT, USA, Oct. 20-24, 2002.
P.Y. Hung, B. Foran, A. Hou, X. Zhang, and C. Oroshiba, “Non-contact electrical characterization of high-dielectric-constant (high-k) materials,” 202nd ECS meeting, Salt Lake City, UT, USA, Oct. 20-24, 2002.
Y. Kim, G. Gebara, M. Freiler, J. Barnett, D. Riley, J. Chen, K. Torres, J. Lim, B. Foran, F. Shaapur, A. Agarwal, P. Lysaght, G. A. Brown, C. Young, S. Borthakur, H. J. Li, B. Nguyen, P. Zeitzoff, G. Bersuker, D. Derro, R. Bergmann, R. W. Murto, A. Hou, H. R. Huff, E. Shero, C. Pomarede, M. Givens, M. Mazanec, and C. Werkhoven, “Conventional n-channel MOSFET devices using single layer HfO2 and ZrO2 as high-k gate dielectrics with polysilicon gate electrode,” International Electron Devices Meeting, pp. 455-458, Washington, DC, USA,, Dec. 2-5, 2001.
M. C. Yu, H. T. Huang, C. H. Chen, M. F. Wang, T. H. Hou, Y. M. Lin, S. M. Jang, C. H. Diaz, J. Sun, Y. K. Fang, S. C. Chen, C. H. Yu, and M. S. Liang “Base oxide scaling limit of thermally-enhanced remote plasma nitridation (TE-RPN) process for ultra-thin gate dielectric formation,” IEEE International Symposium on Semiconductor Manufacturing, pp. 179-182, San Jose, CA, USA, Oct. 8-10, 2001.
H. L. Sun, H. M. Jao, H. T. Huang, J. Y. Pan, T. H. Hou, S. Chen, S. Ramamurthy, E. Chiao, D. Wilusz, and A. Chen “Spike anneal qualification for 0.13 μ m USJ technology on Radiance Centura,” 9th Int. Conf. Adv. Thermal Processing of Semiconductors. RTP 2001, pp. 246-249, Anchorage, AK, USA, Sep. 25-29, 2001.
M. F. Wang, C. H. Chen, M. C. Yu, T. H. Hou, Y. M. Lin, S. C. Chen, Y. K. Fang, C. H. Yu, and M. S. Liang, “Ultrathin ox/nitride gate stack for subuquarter-micro CMOS devices prepared by RTCVD,” IEEE International Symposium on VLSI Technology, Systems, and Applications, pp. 208-211, Hsinchu, Taiwan, Apr. 18-20, 2001.
US Patent
T. H. Hou, M. F. Wang, C. C. Chen, C. W. Yang, L. G. Yao, and S. C. Chen, “Dual gate dielectric scheme: SiON for high performance devices and high k for low power device”, US Patent 6,890,811, May. 10, 2005.
L. G. Yao, M. F. Wang, Y. M. Lin, T. H. Hou, and S. C. Chen, “Chemical vapor deposition (CVD) method employing wetting pre-treatment”, US Patent 6,764,927, Jul. 20, 2004
Y. M. Lin and T. H. Hou, “Layer of high-k inter-poly dielectric”, US Patent 6,753,224, Jun. 22, 2004.
T. H. Hou, M. F. Wang, C. C. Chen, C. W. Yang, L. G. Yao, and S. C. Chen, “Dual gate dielectric scheme: SiON for high performance devices and high k for low power device”, US Patent 6,706,581, Mar. 16, 2004.
